🔧 Verilog plugin for Sublime Text 2/3. It helps to generate a simple testbench, instantiate a module, insert a user-header, repeat codes with formatted incremental/decremental numbers, etc.
☆45Mar 27, 2026Updated 2 months ago
Alternatives and similar repositories for Verilog-Gadget
Users that are interested in Verilog-Gadget are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 👌 This linter plugin for SublimeLinter provides an interface to Verilator (Verilog Simulator)☆16May 14, 2026Updated last month
- This linter plugin for SublimeLinter provides an interface to iverilog (verilog compiler).☆13Apr 16, 2024Updated 2 years ago
- SystemVerilog plugin for Sublime Text☆50Mar 28, 2026Updated 2 months ago
- OPAE porting to Xilinx FPGA devices.☆40Aug 5, 2020Updated 5 years ago
- ☆21Jul 3, 2025Updated 11 months ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- 16QAM modulation and demodulation by Verilog☆21Jan 4, 2021Updated 5 years ago
- my rc files☆12Mar 16, 2016Updated 10 years ago
- ☆89May 4, 2017Updated 9 years ago
- RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator☆10Dec 29, 2021Updated 4 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 7 years ago
- Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)☆23Nov 10, 2024Updated last year
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Mar 10, 2018Updated 8 years ago
- BFM Tester for Chisel HDL☆14Nov 27, 2021Updated 4 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Generate testbench for your verilog module.☆40Apr 3, 2018Updated 8 years ago
- General Purpose Graphics Processing Unit (GPGPU) IP Core☆11Jul 4, 2014Updated 11 years ago
- P4FPGA is located at github.com/hanw/p4fpga☆13Jan 27, 2017Updated 9 years ago
- A DMA Controller for RISCV CPUs☆13Aug 10, 2015Updated 10 years ago
- 基于FPGA的FFT☆19Feb 18, 2019Updated 7 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆36May 12, 2020Updated 6 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- ☆25Oct 8, 2019Updated 6 years ago
- ☆18Jul 9, 2025Updated 11 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Project 2.2 Frequency counter☆12May 30, 2025Updated last year
- Verilog Ethernet Switch (layer 2)☆57Oct 18, 2023Updated 2 years ago
- OpenTSN3.4开源项目的新特性：（1）交换平面深度解耦，硬件代码由TSS（时间敏感交换），HCP（硬件控制点）和OSMAC（Opensync MAC）实现。（2）集成了Opensync开源实现，支持802.1AS和AS6802两种时间同步协议；（3）集成了TSN硬件仿…☆39Aug 13, 2022Updated 3 years ago
- SystemC-WMS (Wave Mixed Signal Simulator) is a class library that extends the standard SystemC kernel to allow modeling and simulation of…☆11Jul 19, 2018Updated 7 years ago
- CNN accelerator using NoC architecture☆18Dec 6, 2018Updated 7 years ago
- There are the documents, floating and fixed-point algorithms, and Verilog codes for the project.☆11Jun 27, 2016Updated 9 years ago
- 最小和算法实现☆10Jul 12, 2020Updated 5 years ago
- This is my MTech Thesis Dissertation Topic.☆10Oct 21, 2022Updated 3 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆21Jun 2, 2026Updated 2 weeks ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆25Nov 2, 2015Updated 10 years ago
- My local copy of UVM-SystemC☆14Apr 27, 2024Updated 2 years ago
- PyMTL3 wrapper of the Berkeley Hardfloat IP☆10Aug 9, 2023Updated 2 years ago
- RoCEv2 hardware implementation in Bluespec SystemVerilog☆36Feb 26, 2026Updated 3 months ago
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 10 years ago
- C Crypto library supporting DES, AES128, SHA256, CCM-AES128, ECDSA, ECDH, PKCS#1 v1.5☆15Jan 24, 2022Updated 4 years ago
- Generate a Verilog Source file and testbench file for a given Moore FSM☆17Nov 18, 2012Updated 13 years ago