CatherineMeng / q-learning-accel-fpga
☆9Updated 4 years ago
Alternatives and similar repositories for q-learning-accel-fpga:
Users that are interested in q-learning-accel-fpga are comparing it to the libraries listed below
- Dataset for ML-guided Accelerator Design☆36Updated 4 months ago
- ☆39Updated 9 months ago
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 4 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆78Updated 8 months ago
- Demonstrating the usage of FGYM: A Toolkit for benchmarking FPGA-accelerated Reinforcement Learning☆13Updated 3 years ago
- High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing☆48Updated 10 months ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆91Updated 3 years ago
- [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs☆17Updated 2 years ago
- ☆54Updated last week
- ☆15Updated 4 years ago
- An end-to-end GCN inference accelerator written in HLS☆19Updated 3 years ago
- ☆63Updated 6 years ago
- ☆70Updated 5 years ago
- A systolic array matrix multiplier☆24Updated 5 years ago
- ☆16Updated 2 years ago
- ☆57Updated 4 years ago
- The open-sourced version of BOOM-Explorer☆39Updated last year
- This project implements a convolution kernel based on vivado HLS on zcu104☆37Updated 5 years ago
- This is a general-purpose simulator for unary computing based on PyTorch, with the paper accepted to ISCA 2020 and awarded IEEE Micro Top…☆42Updated last year
- ☆71Updated 2 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆48Updated 2 weeks ago
- ACM TODAES Best Paper Award, 2022☆22Updated last year
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆51Updated last month
- HISIM introduces a suite of analytical models at the system level to speed up performance prediction for AI models, covering logic-on-log…☆33Updated 3 weeks ago
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- Open-source artifacts and codes of our MICRO'23 paper titled “Sparse-DySta: Sparsity-Aware Dynamic and Static Scheduling for Sparse Multi…☆35Updated last year
- Neural Network Evaluation Tool on Crossbar-based Accelerator with Resistive Memory☆38Updated 5 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆69Updated 5 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- ☆16Updated 6 months ago