SNU-HPCS / NeuroSyncLinks
NeuroSync: A Scalable and Accurate Brain Simulation System using Safe and Efficient Speculation (HPCA 2022)
☆12Updated 2 years ago
Alternatives and similar repositories for NeuroSync
Users that are interested in NeuroSync are comparing it to the libraries listed below
Sorting:
- LoAS: Fully Temporal-Parallel Dataflow for Dual-Sparse Spiking Neural Networks, MICRO 2024.☆11Updated 3 months ago
- I will share some useful or interesting papers about neuromorphic processor☆25Updated 4 months ago
- SATA_Sim is an energy estimation framework for Backpropagation-Through-Time (BPTT) based Spiking Neural Networks (SNNs) training and infe…☆28Updated 9 months ago
- The official implementation of HPCA 2025 paper, Prosperity: Accelerating Spiking Neural Networks via Product Sparsity☆31Updated 5 months ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆51Updated 4 years ago
- ☆16Updated last year
- ☆17Updated 4 years ago
- Framework for radix encoded SNN on FPGA☆13Updated 3 years ago
- [ASP-DAC 2025] "NeuronQuant: Accurate and Efficient Post-Training Quantization for Spiking Neural Networks" Official Implementation☆11Updated 3 months ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆70Updated 3 months ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆34Updated 3 years ago
- Neural Network Evaluation Tool on Crossbar-based Accelerator with Resistive Memory☆40Updated 5 years ago
- ☆17Updated 9 months ago
- A comprehensive tool that allows for system-level performance estimation of chiplet-based In-Memory computing (IMC) architectures.☆21Updated last year
- MICRO22 artifact evaluation for Sparseloop☆44Updated 2 years ago
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆22Updated 4 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆79Updated 3 years ago
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆65Updated 2 years ago
- An energy simulation framework for BPTT-based SNN inference and training.☆16Updated last year
- ☆9Updated last year
- ☆19Updated 4 years ago
- ☆25Updated last year
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆54Updated 3 months ago
- [TVLSI'23] This repository contains the source code for the paper "FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Net…☆19Updated last year
- HW accelerator mapping optimization framework for in-memory computing☆24Updated 3 weeks ago
- MINT, Multiplier-less INTeger Quantization for Energy Efficient Spiking Neural Networks, ASP-DAC 2024, Nominated for Best Paper Award☆14Updated last year
- [TCAD'24] This repository contains the source code for the paper "FireFly v2: Advancing Hardware Support for High-Performance Spiking Neu…☆19Updated last year
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆34Updated 5 years ago
- A list of our chiplet simulaters☆33Updated 2 months ago
- ☆31Updated 4 years ago