SNU-HPCS / NeuroSync
NeuroSync: A Scalable and Accurate Brain Simulation System using Safe and Efficient Speculation (HPCA 2022)
☆8Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for NeuroSync
- I will share some useful or interesting papers about neuromorphic processor☆17Updated 3 months ago
- SATA_Sim is an energy estimation framework for Backpropagation-Through-Time (BPTT) based Spiking Neural Networks (SNNs) training and infe…☆25Updated last month
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆46Updated 3 years ago
- ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.☆77Updated 2 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆54Updated 7 months ago
- ☆41Updated 9 months ago
- MINT, Multiplier-less INTeger Quantization for Energy Efficient Spiking Neural Networks, ASP-DAC 2024, Nominated for Best Paper Award☆10Updated 7 months ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆26Updated 4 months ago
- ☆17Updated 3 years ago
- An energy simulation framework for BPTT-based SNN inference and training.☆14Updated last year
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆121Updated 9 months ago
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆52Updated 3 years ago
- MICRO22 artifact evaluation for Sparseloop☆39Updated 2 years ago
- A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems☆142Updated 6 months ago
- ☆13Updated 3 years ago
- A comprehensive tool that allows for system-level performance estimation of chiplet-based In-Memory computing (IMC) architectures.☆17Updated 4 months ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆56Updated 2 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆30Updated last month
- ☆45Updated 2 months ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆31Updated 2 years ago
- ☆24Updated 7 months ago
- Open-source of MSD framework☆14Updated last year
- CORDIC-SNN, followed with "Unsupervised learning of digital recognition using STDP" published in 2015, frontiers☆20Updated 4 years ago
- ☆31Updated 10 months ago
- ☆15Updated this week
- ☆30Updated 4 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆64Updated 11 months ago
- ☆26Updated 3 years ago
- IEEE Transactions on Circuits and Systems I: Efficient FPGA Implementations of Pair and Triplet-based STDP for Neuromorphic Architectures☆22Updated 5 years ago