Alternatives and similar repositories for riscv-mcu:

Users that are interested in riscv-mcu are comparing it to the libraries listed below

• redlightASl / Notes
  ☆71Updated last month
• OSCPU / ysyx-workbench
  ☆141Updated 6 months ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆148Updated 5 months ago
• ysyx-ta / ysyx-summer-readings
  ☆63Updated 7 months ago
• NJU-ProjectN / nvboard
  NJU Virtual Board
  ☆265Updated 3 months ago
• LoveLonelyTime / Bergamot
  An exquisite superscalar RV32GC processor.
  ☆151Updated 2 months ago
• OSCPU / ysyxSoC
  ☆80Updated last month
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆26Updated 2 years ago
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆128Updated last year
• Yawei-Ding / ysyx_riscv64_cpu
  ☆62Updated last year
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆99Updated 9 months ago
• xiaowuzxc / SparrowRV
  An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.
  ☆60Updated 2 years ago
• OSCPU / yosys-sta
  ☆62Updated 3 months ago
• USTC-System-Courses / CECS-Lab
  ☆34Updated last year
• Xinyang-ZHANG / RISC_V_RV32I_5stage_pipeline
  5 stage pipeline, single cycle risc-V implementation
  ☆21Updated last year
• github-3rr0r / RV32ISC
  A RISC-V RV32I ISA Single Cycle CPU
  ☆23Updated last year
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆63Updated 2 years ago
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆103Updated 2 years ago
• CutestPanda / Opensoc
  包含了SOC设计中的通用IP，如外设、总线结构、基础、验证等
  ☆69Updated last week
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆141Updated 2 years ago
• liuqdev / 8-bits-RISC-CPU-Verilog
  Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
  ☆145Updated 6 years ago
• Azalea8 / riscv_cpu
  riscv指令集，单周期以及五级流水线CPU
  ☆47Updated 2 months ago
• VenciFreeman / RISC-V
  A simple RISC-V CPU written in Verilog.
  ☆62Updated 7 months ago
• shinezyy / micro-arch-training
  How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design
  ☆533Updated 7 months ago
• CustomizableComputingLab / CustomizableComputingLab.github.io
  ☆142Updated last month
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆194Updated this week
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆49Updated 2 years ago
• ISRC-CAS / riscv-isa-manual-cn
  ☆146Updated last year
• Jasonyanyusong / ysyx-npc-workbench
  一生一芯RISCV处理器核代码仓库（包括相关工具）
  ☆12Updated 6 months ago
• Nitcloud / Digital-IDE
  在vscode上的数字设计开发插件
  ☆359Updated 2 years ago