Alternatives and similar repositories for DigitalLogic-Autumn2020

Users that are interested in DigitalLogic-Autumn2020 are comparing it to the libraries listed below

• Azalea8 / riscv_cpu
  riscv指令集，单周期以及五级流水线CPU
  ☆105Updated last year
• fluctlight001 / nscscc2022_single_tools
  龙芯杯个人赛工具包（适用于个人赛的golden_trace工具）
  ☆62Updated last year
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆146Updated last year
• Lyncien / RISC-V-32I
  体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
  ☆86Updated 6 years ago
• cebarobot / UCAS-CALab-mycpu_verify
  计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab3-Lab9
  ☆34Updated 4 years ago
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆33Updated 3 years ago
• MAdrid1011 / USTC-NSCSCC
  中国科学技术大学龙芯杯参赛作品仓库合集
  ☆15Updated last year
• Yawei-Ding / ysyx_riscv64_cpu
  ☆72Updated 2 years ago
• 15947470421 / digital_IC_experiment
  我设计了一些数字集成电路的教学实验，供大家学习~
  ☆35Updated 11 months ago
• Groupsun / riscv-mini-five-stage
  This is my graduation project, a simple processor soft core, which implements RV32I ISA.
  ☆16Updated 6 years ago
• zhhangBian / BOOM_chip
  乱序双发处理器，在2024年计算机系统能力大赛CPU赛道（龙芯杯）获二等奖，全国第四
  ☆16Updated last year
• loongson-education / nscscc-wiki
  NSCSCC 信息整合
  ☆253Updated 4 years ago
• NJU-ProjectN / nvboard
  NJU Virtual Board
  ☆297Updated 4 months ago
• qing-2 / CPU
  单周期 8指令 MIPS32CPU
  ☆96Updated last week
• fluctlight001 / cpu_for_nscscc2022_single
  2022年龙芯杯个人赛 单发射110M（含icache）
  ☆47Updated 3 years ago
• doonny / basic_knowledge
  Things to learn for new students in the Lab for AI chips and systems of BJTU .
  ☆258Updated last year
• Kristoff-starling / ProjectN-CPU
  Single Cycle and Pipeline CPU of RISC-V Architecture designed for Digital Design and Computer Organization Experiments 2021, NJU
  ☆14Updated 3 years ago
• liuqdev / 8-bits-RISC-CPU-Verilog
  Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
  ☆160Updated 6 years ago
• cebarobot / UCAS-Computer-Architecture-Lab
  计算机体系结构研讨课 2020秋季 UCAS 《CPU设计实战》 工程环境及 RTL 代码合集
  ☆18Updated 4 years ago
• Silverster98 / bit_nscscc_suggestion
  为了更好地帮助后来的同学参加龙芯杯，草拟了这份建议，望对后来人有所帮助
  ☆134Updated 5 years ago
• OSCPU / ysyx-workbench
  ☆160Updated 3 weeks ago
• EricJin2002 / UCAS-CA-2022
  一个单发射五级静态流水CPU，采用龙芯32位精简版指令集，支持异常和中断处理，使用AXI总线接口，已集成TLB模块
  ☆16Updated 3 years ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆193Updated last year
• ysyx-ta / ysyx-summer-readings
  ☆67Updated last year
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆127Updated last year
• spokeyjoe / LoongArchCPU
  A LoongArch pipeline CPU. Project of Computer Architecture Lab @UCAS.
  ☆30Updated last year
• renyangang / riscv-mcu
  This project utilizes the Digital circuit simulation software,to build a CPU that supports a simple instruction set and simple peripheral…
  ☆77Updated 9 months ago
• lvyufeng / step_into_mips
  一步一步写MIPS CPU
  ☆848Updated 4 years ago
• fluctlight001 / cpu_for_nscscc2020
  2020龙芯杯个人赛 简易双发射60M（含ibuffer）
  ☆41Updated 5 years ago
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆136Updated 2 years ago