Alternatives and similar repositories for pynq

Users that are interested in pynq are comparing it to the libraries listed below

• riscv / riscv-cheri
  This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…
  ☆72Updated this week
• POETSII / tinsel
  Manythread RISC-V overlay for FPGA clusters
  ☆38Updated 2 years ago
• charlottia / hdx
  HDL development environment on Nix.
  ☆26Updated 8 months ago
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆312Updated last week
• benpye / nix-fpga-tools
  ☆23Updated 3 years ago
• pc2 / sus-compiler
  A new Hardware Design Language that keeps you in the driver's seat
  ☆112Updated this week
• ghdl / ghdl-language-server
  Language server based on ghdl
  ☆95Updated 2 months ago
• sifferman / schematics
  Examples of how to Generate Schematics from SystemVerilog Synthesis Tools
  ☆22Updated last year
• mit-plv / koika
  A core language for rule-based hardware design 🦑
  ☆157Updated last month
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 3 years ago
• hdl / bazel_rules_hdl
  Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (htt…
  ☆135Updated last month
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆60Updated last week
• tomverbeure / gdbwave
  GDB server to debug CPU simulation waveform traces
  ☆44Updated 3 years ago
• mosscomp / moss
  A computer for human beings.
  ☆44Updated 8 months ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆397Updated 6 months ago
• thoughtpolice / rv32-sail
  32-bit RISC-V Emulator
  ☆25Updated 6 years ago
• fabianschuiki / llhd
  Low Level Hardware Description — A foundation for building hardware design tools.
  ☆420Updated 3 years ago
• anishathalye / knox
  A framework for formally verifying hardware security modules to be free of hardware, software, and timing side-channel vulnerabilities 🔏
  ☆35Updated 5 months ago
• fabianschuiki / moore
  A hardware compiler based on LLHD and CIRCT
  ☆261Updated 2 weeks ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆155Updated last month
• rsnikhil / ICFP2020_Bluespec_Tutorial
  Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference
  ☆73Updated 2 years ago
• CTSRD-CHERI / bluecheck
  A generic test bench written in Bluespec
  ☆53Updated 4 years ago
• B-Lang-org / bsc-contrib
  A place to share libraries and utilities that don't belong in the core bsc repo
  ☆36Updated 4 months ago
• cucapra / filament
  Fearless hardware design
  ☆177Updated last week
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆461Updated last week
• psurply / dwfv
  A simple digital waveform viewer with vi-like key bindings.
  ☆138Updated 4 months ago
• dalance / svlint
  SystemVerilog linter
  ☆353Updated last week
• zachbe / digial-ising
  An all-digital, ring-oscillator-based Ising solver.
  ☆17Updated last year
• pascalkuthe / OpenVAF
  An innovative Verilog-A compiler
  ☆161Updated 10 months ago