Alternatives and similar repositories for FPGA-Verilog

Users that are interested in FPGA-Verilog are comparing it to the libraries listed below

• mbaykenar / apis_anatolia
  "Mehmet Burak Aykenar" YouTube kanalında yayınlanan VHDL ve FPGA dersleri ile ilgili kodları içermektedir.
  ☆103Updated 11 months ago
• TUTEL-TUBITAK / TEKNOFEST_2023_Cip_Tasarim_Yarismasi
  Bu depo TEKNOFEST 2023 Çip Tasarım Yarışması'nda Analog Tasarım ve Sayısal İşlemci Tasarımı kategorilerinde çeşitli dosyaları paylaşmak i…
  ☆21Updated 2 years ago
• koraykarakurt / FPGA-from-Zero-to-Hero
  Repository of FPGA from Zero to Hero - Live and Free FPGA/SoC Lectures on YouTube (www.youtube.com/@falsepaths)
  ☆33Updated 2 months ago
• sudhamshu091 / Single-Cycle-Risc-Processor-32-bit-Verilog
  Single Cycle RISC MIPS Processor
  ☆33Updated 3 years ago
• rajdeep66 / edaBundle_whyRD
  opensource EDA tool flor VLSI design
  ☆33Updated last year
• mehwish411 / 5-Staged-Pipelined-RISC-V-32I-Processor
  5 stage pipeline implementation of RISC-V 32I Processor.
  ☆11Updated 6 months ago
• kerimturak / tcore-rv32imc
  ☆12Updated 2 months ago
• kirbyydoge / kasirga_gok_2023
  Kasırga - Gök Sayısal İşlemci Kategorisi RISC-V İşlemci Tasarımı
  ☆16Updated 2 years ago
• Marco-Winzker / FPGA-FIR-Filter
  Lecture about FIR filter on an FPGA
  ☆12Updated last year
• semiDESIgner / 50daysRTLcode
  ☆17Updated 2 years ago
• OrsuVenkataKrishnaiah1235 / RTL-Coding
  "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
  ☆15Updated last year
• Arjun-Narula / Traffic-Light-Controller-using-Verilog
  the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.
  ☆42Updated 4 years ago
• TheSUPERCD / 8bit_MicroComputer_Verilog
  This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…
  ☆56Updated 2 years ago
• D-curs-D / Inverter-design-and-analysis-using-sky130pdk
  Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools
  ☆110Updated 3 years ago
• FPGADude / Digital-Design
  Verilog HDL files
  ☆141Updated last year
• ItzzInfinity / 100-days-of-RTL
  Trying to get a new skill
  ☆23Updated 5 months ago
• yusfux / KASIRGA-GUN
  KASIRGA-GUN | RV32IMCX
  ☆12Updated 9 months ago
• adibis / Interrupt_Controller
  An 8 input interrupt controller written in Verilog.
  ☆26Updated 13 years ago
• yigitbektasgursoy / Electronics_and_Communication_Engineering_ITU
  You can find the documents, assignments and projects of some of the courses given in Electronics and Communication engineering at Istanbu…
  ☆64Updated 11 months ago
• karribharathi / 100-Days-of-RTL
  ☆16Updated last year
• sudhamshu091 / Single-Cycle-Risc-Pipelined-Processor-Verilog
  Single Cycle MIPS Pipelined Processor using Verilog
  ☆14Updated 3 years ago
• sure-trust / VLSI-Project-AXI-to-APB-Bridge
  ☆19Updated last year
• KOTHAVANI / 100-Days-of-RTL-code
  ☆41Updated last year
• fayizferosh / yosys-tcl-ui-report
  5 Day TCL begginer to advanced training workshop by VSD
  ☆17Updated last year
• iamrk-vlsi / RISC-V-MYTH-Workshop
  5 days (30 hours) is all what took me to learn the basics and design a pipelined RV32I core. Check this article to know more !
  ☆12Updated 3 years ago
• ekb0412 / 100DaysofRTL
  "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
  ☆78Updated last year
• georgeyhere / FPGA-Video-Processing
  Realtime video processing w/ Gaussian + Sobel Filters targeting Artix-7 FPGA
  ☆26Updated 3 years ago
• Ummidichandrika / 100-Days-of-RTL
  ☆111Updated last year
• muhammedkocaoglu / mystic_riscv64
  64-bit RISC-V processor
  ☆16Updated 2 years ago
• Manish4403 / RISC_V_with_ICACHE
  ☆12Updated 6 months ago