A set of standalone kernel modules and userspace library for using the AXI DMA on a Zynq MPSoC
☆22Feb 22, 2020Updated 6 years ago
Alternatives and similar repositories for mpsoc_axidma
Users that are interested in mpsoc_axidma are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- MPSoC architecture for accelerating drone components and interfacing with ROS2.☆20May 12, 2025Updated last year
- IP core with AXI interface for reading the Device DNA from the PL of Zynq 7000 devices☆14Nov 25, 2021Updated 4 years ago
- Generates simple AXI4-lite IP for use in Vivado from register specifications☆16Oct 13, 2026Updated 2 weeks ago
- Generic AXI interconnect fabric☆13Jul 17, 2014Updated 12 years ago
- Business Rule Engine Hardware Accelerator☆15Jun 18, 2020Updated 6 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- ☆17Jun 5, 2024Updated 2 years ago
- Hardware, Linux Driver and Library for the Zynq AXI DMA interface☆107Jul 21, 2018Updated 8 years ago
- Project and presentation for SpaceX Application☆14Jul 21, 2017Updated 9 years ago
- SystemVerilog Logger☆19Apr 6, 2026Updated 6 months ago
- A Python module to interact with an Intel JTAG UART☆17May 8, 2021Updated 5 years ago
- Verilog Examples and WebFPGA Standard Library☆11Nov 25, 2019Updated 6 years ago
- Docker Development Environment for SpinalHDL☆20Aug 8, 2024Updated 2 years ago
- ☆13Apr 24, 2022Updated 4 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆42May 17, 2022Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Saleae Logic Dshot (ESC protocol) Plugin☆11Apr 10, 2024Updated 2 years ago
- Modular Multi-ported SRAM-based Memory☆33Nov 8, 2024Updated last year
- An arduino air management system to control an air suspension in a car.☆10Aug 24, 2019Updated 7 years ago
- Test SRIO connection between FPGA (Kintex-7) and DSP (C6678)☆20Nov 10, 2017Updated 8 years ago
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆22Feb 4, 2025Updated last year
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆45Aug 10, 2022Updated 4 years ago
- Userspace DMA library for Zynq-based SoCs☆16Jan 22, 2019Updated 7 years ago
- OscillatorIMP ecosystem FPGA IP sources☆28Feb 22, 2026Updated 8 months ago
- Example projects for snickerdoodle☆29Jan 23, 2026Updated 9 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Low Precision Arithmetic Simulation in PyTorch - extension for posit and beyond☆16Dec 9, 2025Updated 10 months ago
- A Fitbit OS app for tracking snow activities in the Fitbit activity log.☆11Jan 4, 2021Updated 5 years ago
- LaTeX document class for electronics datasheets☆10Apr 17, 2021Updated 5 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆15Nov 9, 2014Updated 11 years ago
- FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq Ultrascale+ MPSoC)☆136Aug 14, 2025Updated last year
- Automate device under test hardware for testing, quality control and manufacturing.☆13Updated this week
- Public resources available for Xilinx MPSOC+ and SDSOC hardware☆18May 26, 2017Updated 9 years ago
- ROS 2 Hardware Acceleration Working Group community governance model & list of projects☆71Jan 4, 2024Updated 2 years ago
- Four versions of MIPS 32bit implemented in Verilog using Vivado, ready for Simulation and Nexys4 DDR Board☆13Sep 15, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Sample minimal Vivado project for Parallella FPGA☆47May 15, 2016Updated 10 years ago
- OpenEmbedded/Yocto layer for topic products. Contains BSP for Miami boards and Florida carriers.☆16Oct 13, 2026Updated 2 weeks ago
- Secure OTA bootloader for SiLabs EFR32BG BLE chips and BGM111 modules☆12Apr 21, 2017Updated 9 years ago
- Octave/MATLAB code for generating compensation FIR coefficients☆14Sep 7, 2015Updated 11 years ago
- System Design in Python (SyDPy) is a tool for design and verification of concurrent systems. The tool is offered as an alternative to Sys…☆12Jun 2, 2016Updated 10 years ago
- Snickerdoodle board from krtl with PYNQ☆13Nov 17, 2019Updated 6 years ago
- ☆17Apr 25, 2024Updated 2 years ago