tud-ccc / CinnamonLinks
☆28Updated last week
Alternatives and similar repositories for Cinnamon
Users that are interested in Cinnamon are comparing it to the libraries listed below
Sorting:
- ☆31Updated 3 years ago
- agile hardware-software co-design☆47Updated 3 years ago
- HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs☆34Updated 5 months ago
- EQueue Dialect☆40Updated 3 years ago
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆118Updated 3 months ago
- Release of stream-specialization software/hardware stack.☆121Updated 2 years ago
- This GitHub repo contains the artifact for CPElide, which appears at MICRO '24☆11Updated 8 months ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆53Updated 2 months ago
- ☆69Updated 11 months ago
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆64Updated 2 years ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆67Updated 2 months ago
- Artifact material for [HPCA 2025] #2108 "UniNDP: A Unified Compilation and Simulation Tool for Near DRAM Processing Architectures"☆24Updated 6 months ago
- NeuPIMs: NPU-PIM Heterogeneous Acceleration for Batched LLM Inferencing☆83Updated 11 months ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆36Updated last year
- ☆91Updated last year
- ☆53Updated 2 months ago
- ☆25Updated 3 years ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆55Updated 3 years ago
- MICRO22 artifact evaluation for Sparseloop☆43Updated 2 years ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆80Updated last month
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- OSDI 2023 Welder, deeplearning compiler☆19Updated last year
- PIMeval simulator and PIMbench suite☆27Updated last week
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆79Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- Artifact for paper "PIM is All You Need: A CXL-Enabled GPU-Free System for LLM Inference", ASPLOS 2025☆63Updated last month
- DAMOV is a benchmark suite and a methodical framework targeting the study of data movement bottlenecks in modern applications. It is inte…☆81Updated last year
- ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines (FPGA 2025 Best Paper Nominee)☆27Updated this week
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆37Updated 2 years ago
- A PIM instrumentation, compilation, execution, simulation, and evaluation repository for BLIMP-style architectures.☆18Updated 3 years ago