0BAB1 / BRH_TutorialsLinks
[BRH YT CHANNEL] This repo contains all the code and ressources you need for the Zynq tutorials, ready to copy and paste.
☆64Updated 3 months ago
Alternatives and similar repositories for BRH_Tutorials
Users that are interested in BRH_Tutorials are comparing it to the libraries listed below
Sorting:
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆64Updated 11 months ago
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆149Updated 4 years ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆415Updated last week
- ☆106Updated 2 years ago
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆88Updated 4 months ago
- A huge collection of VHDL/Verilog open-source IP cores scraped from the web☆118Updated 9 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆112Updated last year
- Learn how to build our own RV32I core, verify it and actually use it. From scratch & with more than 200 pages of detailed tutorial with s…☆234Updated this week
- SD-Card controller, using either SPI, SDIO, or eMMC interfaces☆317Updated 5 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆117Updated last week
- ☆73Updated last year
- Simple 8-bit UART realization on Verilog HDL.☆110Updated last year
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆141Updated this week
- Verilog implementation of multi-stage 32-bit RISC-V processor☆129Updated 4 years ago
- Opensource software/hardware platform to build edge AI solutions deployed on FPGA or custom ASIC hardware.☆270Updated 6 months ago
- Opensource DDR3 Controller☆387Updated 3 months ago
- A Reconfigurable RISC-V Core for Approximate Computing☆125Updated 4 months ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆51Updated last year
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆141Updated this week
- Curriculum for a university course to teach chip design using open source EDA tools☆110Updated last year
- A simple implementation of a UART modem in Verilog.☆157Updated 3 years ago
- This repository contains the codebase for Virtual FPGA Lab in Makerchip contributing as a participant in Google Summer of Code 2021, unde…☆219Updated 4 months ago
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆272Updated 4 months ago
- Arduino compatible Risc-V Based SOC☆156Updated last year
- ☆350Updated 2 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆80Updated last year
- 10Gb Ethernet Switch☆231Updated last week
- Linux capable RISC-V SoC designed to be readable and useful.☆152Updated 4 months ago
- Verilog HDL files☆153Updated last year
- SystemVerilog Tutorial☆176Updated this week