Alternatives and similar repositories for BRH_Tutorials:

Users that are interested in BRH_Tutorials are comparing it to the libraries listed below

• Kobzon86 / Convolutional-Neural-Network-using-SystemVerilog
  Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
  ☆58Updated 5 months ago
• bl0x / learn-fpga-amaranth
  Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL
  ☆102Updated 8 months ago
• HDLForBeginners / Toolbox
  ☆68Updated 8 months ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆83Updated last year
• HDLForBeginners / Examples
  ☆92Updated last year
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆101Updated 11 months ago
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆335Updated this week
• kiwih / qtcore-C1
  ☆44Updated last year
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆97Updated 4 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆66Updated this week
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆45Updated last year
• 0BAB1 / HOLY_CORE_COURSE
  Learn how to build our own RV32I core and use it on FPGA.
  ☆121Updated this week
• georgeyhere / Toast-RV32i
  Pipelined RISC-V RV32I Core in Verilog
  ☆38Updated 2 years ago
• PyFPGA / pyfpga
  A Python package to use FPGA development tools programmatically.
  ☆128Updated 3 weeks ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆80Updated this week
• viktor-nikolov / MicroBlaze-DDR3-tutorial
  Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application
  ☆45Updated 10 months ago
• Marco-Winzker / NN_RGB_FPGA
  FPGA Design of a Neural Network for Color Detection
  ☆75Updated 2 months ago
• klyone / opencores-ip
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆91Updated 9 years ago
• tscheipel / HaDes-V
  HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…
  ☆45Updated 2 months ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆90Updated 7 months ago
• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆124Updated 3 years ago
• asinghani / open-eda-course
  Curriculum for a university course to teach chip design using open source EDA tools
  ☆64Updated last year
• TinyTapeout / tt06-verilog-template
  Submission template for Tiny Tapeout 6 - Verilog HDL Projects
  ☆32Updated 11 months ago
• aignacio / nox
  RISC-V Nox core
  ☆62Updated 3 weeks ago
• ulixxe / usb_cdc
  Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
  ☆166Updated last year
• adonairc / tt07-dda-van-der-pol
  DDA solver for the van der Pol oscillator using 16-bit posits
  ☆28Updated 2 months ago
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆61Updated this week
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆127Updated 3 years ago
• getinstachip / vpm
  Verilog package manager written in Rust
  ☆143Updated 6 months ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆73Updated this week