0BAB1 / BRH_TutorialsLinks
[BRH YT CHANNEL] This repo contains all the code and ressources you need for the Zynq tutorials, ready to copy and paste.
☆53Updated 3 weeks ago
Alternatives and similar repositories for BRH_Tutorials
Users that are interested in BRH_Tutorials are comparing it to the libraries listed below
Sorting:
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆97Updated 2 weeks ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆58Updated 6 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆91Updated last year
- ☆93Updated last year
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆45Updated last year
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆46Updated this week
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆51Updated 4 months ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆77Updated last year
- A huge collection of VHDL/Verilog open-source IP cores scraped from the web☆102Updated 9 years ago
- Verilog implementation of multi-stage 32-bit RISC-V processor☆106Updated 4 years ago
- Simple 8-bit UART realization on Verilog HDL.☆105Updated last year
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆130Updated 3 years ago
- FPGA Design of a Neural Network for Color Detection☆76Updated 3 months ago
- ☆44Updated last year
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆89Updated this week
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆91Updated last year
- PQR5ASM is a RISC-V Assembler compliant with RV32I☆19Updated last month
- RISC-V microcontroller IP core developed in Verilog☆173Updated last month
- This repository contains the design files of RISC-V Single Cycle Core☆47Updated last year
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆93Updated 9 months ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆116Updated 4 years ago
- ☆72Updated 9 months ago
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆105Updated 10 months ago
- Opensource DDR3 Controller☆333Updated last week
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆169Updated last year
- Raptor end-to-end FPGA Compiler and GUI☆78Updated 5 months ago
- Universal Memory Interface (UMI)☆145Updated this week
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 5 months ago
- RISC-V Nox core☆62Updated 2 months ago
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆88Updated 4 months ago