Alternatives and similar repositories for OV7670_NEXYS4_Verilog:

Users that are interested in OV7670_NEXYS4_Verilog are comparing it to the libraries listed below

• westonb / OV7670-Verilog
  Verilog modules required to get the OV7670 camera working
  ☆65Updated 6 years ago
• AngeloJacobo / FPGA_OV7670_Camera_Interface
  Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps
  ☆57Updated 3 years ago
• adibis / DDR2_Controller
  DDR2 memory controller written in Verilog
  ☆72Updated 12 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆52Updated 10 years ago
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆53Updated 2 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆48Updated 5 years ago
• teekamkhandelwal / asynchronous_fifo
  Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.
  ☆31Updated 3 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆61Updated 4 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆31Updated 2 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆60Updated 3 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆47Updated 3 years ago
• xupgit / Zynq-Design-using-Vivado
  This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.
  ☆81Updated last year
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆21Updated last year
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆32Updated 8 years ago
• freecores / robust_axi2ahb
  Generic AXI to AHB bridge
  ☆16Updated 10 years ago
• vritrv / ROUTER-1X3-RTL-DESIGN
  Architectural design of data router in verilog
  ☆28Updated 5 years ago
• JAYRAM711 / 100-DAYS-OF-RTL
  This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…
  ☆17Updated last year
• freecores / round_robin_arbiter
  round robin arbiter
  ☆70Updated 10 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆48Updated 8 months ago
• abdelazeem201 / ASIC-implementation-of-AES
  Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…
  ☆20Updated 3 years ago
• ishfaqahmed29 / FIFO_UVM_Verification
  Synchronous FIFO Testbench
  ☆10Updated 2 years ago
• shubhi704 / APB-Protocol
  ☆38Updated 3 years ago
• bmartini / verilog-arbiter
  A look ahead, round-robing parametrized arbiter written in Verilog.
  ☆41Updated 4 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆88Updated 4 years ago
• ptracton / AXI_BFM
  AXI4 BFM in Verilog
  ☆31Updated 8 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆38Updated 2 years ago
• mitshine / UVM-and-System-Verilog-Manual
  UVM and System Verilog Manuals
  ☆39Updated 5 years ago
• sudhamshu091 / Single-Cycle-Risc-Processor-32-bit-Verilog
  Single Cycle RISC MIPS Processor
  ☆31Updated 3 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆85Updated 5 years ago