canerpotur / FPGALinks
This repository includes some FPGA projects like VGA control, image processing. So far, fpga can drive a VGA monitor and display an image on a VGA monitor.
☆14Updated 8 years ago
Alternatives and similar repositories for FPGA
Users that are interested in FPGA are comparing it to the libraries listed below
Sorting:
- OpenExSys_NoC a mesh-based network on chip IP.☆15Updated last year
- DMA core compatible with AHB3-Lite☆10Updated 6 years ago
- ☆11Updated 2 years ago
- Verification IP for Watchdog☆11Updated 4 years ago
- 位宽和深度可定制的异步FIFO☆13Updated last year
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆14Updated last year
- UVM Testbench for synchronus fifo☆17Updated 4 years ago
- A human detection system is developed on Matlab and FPGA: The 130x66 RGB pixels of static input image was attracted features and classifi…☆11Updated 2 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Updated 9 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆12Updated 5 years ago
- UVM testbench for verifying the Pulpino SoC☆14Updated 5 years ago
- ☆13Updated 2 years ago
- ☆17Updated 10 years ago
- ☆16Updated 6 years ago
- CORDIC VLSI-IP for deep learning activation functions☆15Updated 6 years ago
- Direct Access Memory for MPSoC☆13Updated 2 months ago
- Superscalar Out-of-Order NPU Design on FPGA☆10Updated last year
- verification of simple axi-based cache☆18Updated 6 years ago
- 包括同步FIFO(输入输出位宽相同),异步FIFO(输入输出位宽相同),异步FIFO(能实现输出数据位宽是输入数据位宽的1/2或2倍)☆20Updated 2 years ago
- ☆12Updated 9 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆23Updated 5 years ago
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆14Updated 10 months ago
- Simple demo showing how to use the ping pong FIFO☆15Updated 9 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆13Updated 2 years ago
- Router 1 x 3 verilog implementation☆14Updated 3 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Updated 6 years ago
- 基于FPGA的FFT☆19Updated 6 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Updated 9 years ago
- AXI4 with a FIFO integrated with VIP☆21Updated last year