Harry-Chen / fpga-virtual-consoleLinks
VT220-compatible console on Cyclone IV EP4CE55F23I7
☆43Updated 7 years ago
Alternatives and similar repositories for fpga-virtual-console
Users that are interested in fpga-virtual-console are comparing it to the libraries listed below
Sorting:
- A extremely size-optimized RV32I soft processor for FPGA.☆28Updated 7 years ago
- Trivial RISC-V Linux binary bootloader☆51Updated 4 years ago
- Tang Mega 138K Pro examples☆76Updated 2 weeks ago
- HDMI core in Chisel HDL☆51Updated last year
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆63Updated 3 years ago
- This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…☆89Updated 4 years ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆61Updated 2 months ago
- SoftCPU/SoC engine-V☆54Updated 5 months ago
- Portable HyperRAM controller☆57Updated 8 months ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- PicoRV☆44Updated 5 years ago
- Linux capable RISC-V SoC designed to be readable and useful.☆151Updated 2 months ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆124Updated 9 years ago
- Remote JTAG server for remote debugging☆40Updated last year
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- Python module containing verilog files for rocket cpu (for use with LiteX).☆14Updated 2 months ago
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- GDB server to debug CPU simulation waveform traces☆44Updated 3 years ago
- An SoC with multiple RISC-V IMA processors.☆19Updated 7 years ago
- Baremetal softwares for TrivialMIPS platform☆11Updated 6 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆80Updated last year
- ☆53Updated 3 years ago
- shdl6800: A 6800 processor written in SpinalHDL☆26Updated 5 years ago
- Naive Educational RISC V processor☆87Updated last month
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆65Updated 7 years ago
- Reverse engineering the XC2064 FPGA☆78Updated 4 years ago
- Small footprint and configurable Inter-Chip communication cores☆60Updated last month
- Basic USB 1.1 Host Controller for small FPGAs☆91Updated 5 years ago