Alternatives and similar repositories for FastCap2

Users that are interested in FastCap2 are comparing it to the libraries listed below

• ediloren / FastHenry2
  FastHenry is the premium inductance solver originally developed at M.I.T. on Unix platform. A de-facto golden reference standard, FastHen…
  ☆72Updated 6 years ago
• ediloren / FasterCap
  FasterCap is a powerful three- and two-dimensional capactiance extraction program.
  ☆34Updated 6 years ago
• dwarning / VA-Models
  Verilog-A simulation models
  ☆91Updated 3 months ago
• wrcad / xictools
  XicTools: Xic graphical editor, WRspice circuit simulator, and accessories. for electronic design.
  ☆180Updated 2 months ago
• thesourcerer8 / OpenSourceTCAD
  Easy access to OpenSource TCAD Tools
  ☆42Updated last month
• Qucs / ADMS
  ADMS is a code generator for some of Verilog-A
  ☆103Updated 3 years ago
• capn-freako / PyBERT
  Serial communication link bit error rate tester simulator, written in Python.
  ☆120Updated this week
• ediloren / EM-Workbench-for-FreeCAD
  This project is dedicated to building an ElectroMagnetic workbench for FreeCAD. FreeCAD is a free 3D parametric CAD. FreeCAD is used as p…
  ☆65Updated last year
• capn-freako / PyAMI
  Python package for IBIS-AMI model development and testing
  ☆33Updated last week
• yuchsiao / caplet
  GDS visualization, geometry analysis, and parallelized capacitance extraction at field-solver accuracy. MS thesis project.
  ☆25Updated last year
• iic-jku / klayout-pex
  Parasitic Extraction for KLayout
  ☆37Updated 2 weeks ago
• jaijeet / MAPP
  The Berkeley Model and Algorithm Prototyping Platform
  ☆22Updated last year
• ACMmodel / MOSFET_model
  A simple MOSFET model with only 5-DC-parameters for circuit simulation
  ☆50Updated 4 months ago
• gmagno / spyci
  A tiny Python package to parse spice raw data files.
  ☆53Updated 3 years ago
• patrickschulz / openPCells
  Parametric layout generator for digital, analog and mixed-signal integrated circuits
  ☆70Updated this week
• arpadbuermen / OpenVAF
  An innovative Verilog-A compiler - reloaded
  ☆37Updated 2 weeks ago
• purdue-onchip / gds2Para
  GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
  ☆129Updated 2 years ago
• bluecheetah / bag
  BAG framework
  ☆41Updated last year
• hohlraum / gdsCAD
  A simple but powerful Python package for creating photolithography masks in the GDSII format.
  ☆95Updated 2 years ago
• kevjzheng / JLSD
  ☆24Updated last year
• ChrisZonghaoLi / gm_id_gf180mcu
  This repo contains introduction of gm/id method and its application to some OTA design examples.
  ☆18Updated 2 years ago
• dan-fritchman / Netlist
  Parsing and generating popular formats of circuit netlist
  ☆39Updated 3 years ago
• cogenda / Genius-TCAD-Open
  Open-source version of the Genius Semiconductor Device Simulator
  ☆157Updated 5 years ago
• ggventurini / python-deltasigma
  A port of the MATLAB Delta Sigma Toolbox based on free software and very little sleep
  ☆95Updated 3 years ago
• MatBucher / ekv3model
  ☆19Updated last year
• The-OpenROAD-Project / OpenRCX
  ☆24Updated 5 years ago
• gdsfactory / skywater130
  skywater 130nm pdk
  ☆41Updated this week
• cogenda / pyEDA
  A python framework for EDA applications.
  ☆37Updated 14 years ago
• dan-fritchman / Hdl21
  Hardware Description Library
  ☆88Updated last week
• Lenty / SLiCAP_python
  Open-source version of SLiCAP, implemented in python
  ☆37Updated last year