xupsh / Amp-zynq
Simple AMP Running Linux and Bare-Metal System on Both Zynq SoC Processors
☆20Updated 9 years ago
Alternatives and similar repositories for Amp-zynq:
Users that are interested in Amp-zynq are comparing it to the libraries listed below
- mirror of https://git.elphel.com/Elphel/x393_sata☆33Updated 4 years ago
- ☆22Updated 8 years ago
- ☆17Updated 4 years ago
- Connecting FPGA and MCU using Ethernet RMII☆23Updated 9 years ago
- Simple C snippet to transfer DMA memory with scatter/gather on a Zynq 7020☆54Updated 7 years ago
- ☆17Updated last year
- 本信号处理板主要由FPGA芯片和CYUSB3.0 芯片组成,其中FPGA模块主要完成与相关外设的交互,CYUSB3.0主要完成协议数据的传输。 2.2.1 FPGA模块 处理流程: 1. 链路初始化: 在上位机完成USB固件的下载,并读取…☆25Updated 9 years ago
- ☆18Updated 9 years ago
- Xilinx Virtual Cable server written in python connecting Xilinx with different JTAG adapters☆11Updated 11 years ago
- Small footprint and configurable JESD204B core☆41Updated 2 months ago
- development interface mil-std-1553b for system on chip☆21Updated 7 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated last year
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆34Updated 7 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆43Updated 9 years ago
- This is a wiki and code sharing for ZYNQ☆71Updated 8 years ago
- How to configure Debian Linux environment for Xilinx Zynq.☆31Updated 8 years ago
- ☆14Updated 8 years ago
- VHDL PCIe Transceiver☆28Updated 4 years ago
- FMC card to allow interfacing Xilinx FPGA boards with Jetson TX2 or TX1 via CSI-2 camera interface☆16Updated last year
- JESD204B core for Migen/MiSoC☆36Updated 3 years ago
- Altera Cyclone IV FPGA project for the PCIe LimeSDR board☆38Updated 2 years ago
- an abstraction layer across user-space Linux, baremetal, and RTOS environments☆24Updated 4 months ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆35Updated 5 years ago
- Open Source ZYNQ Board☆31Updated 9 years ago
- Verilog IP Cores & Tests☆13Updated 6 years ago
- an sata controller using smallest resource.☆15Updated 11 years ago
- Example project that uses the AXI DMA peripheral to connect a custom AXI-Stream peripheral to memory☆13Updated 11 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆32Updated 7 years ago
- MIPI CSI-2 RX☆31Updated 3 years ago
- minimal code to access ps DDR from PL☆19Updated 5 years ago