xupsh / Amp-zynq
Simple AMP Running Linux and Bare-Metal System on Both Zynq SoC Processors
☆20Updated 8 years ago
Related projects ⓘ
Alternatives and complementary repositories for Amp-zynq
- Connecting FPGA and MCU using Ethernet RMII☆22Updated 8 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆33Updated 4 years ago
- Triple Modular Redundancy☆23Updated 5 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated 10 months ago
- Fork of OpenCores jpegencode with Cocotb testbench☆42Updated 9 years ago
- Small footprint and configurable JESD204B core☆40Updated last month
- ☆17Updated last year
- ☆15Updated 8 years ago
- AXI MIPI CSI2 RX FPGA core and kernel driver☆18Updated 9 years ago
- ☆17Updated 9 years ago
- ☆22Updated 8 years ago
- Extensible FPGA control platform☆53Updated last year
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆34Updated 7 years ago
- development interface mil-std-1553b for system on chip☆19Updated 6 years ago
- an sata controller using smallest resource.☆15Updated 10 years ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆35Updated 5 years ago
- This is a wiki and code sharing for ZYNQ☆71Updated 8 years ago
- How to configure Debian Linux environment for Xilinx Zynq.☆30Updated 7 years ago
- ☆15Updated 4 years ago
- Simple C snippet to transfer DMA memory with scatter/gather on a Zynq 7020☆52Updated 7 years ago
- This repository contains source code for Universal boot loader This repository contains source code for Universal boot loader for use wit…☆12Updated last year
- Register-based and RAM-based FIFOs designed in Verilog/System Verilog.☆14Updated 2 months ago
- Generic Logic Interfacing Project☆44Updated 4 years ago
- This repository contains a set of examples of opencl code that can run on the zedboard zynq all programmable soc.☆15Updated 8 years ago
- JESD204B core for Migen/MiSoC☆36Updated 3 years ago
- iDEA FPGA Soft Processor☆14Updated 8 years ago
- FreeRTOS/lwIP (XAPP1026) for Xilinx Zynq devices using Vivado 2016.1. This port is compatible with Xilinx Vivado 2016.1 and was tested on…☆14Updated 7 years ago
- VHDL PCIe Transceiver☆26Updated 4 years ago
- minimal code to access ps DDR from PL☆19Updated 5 years ago
- Xilinx Virtual Cable server written in python connecting Xilinx with different JTAG adapters☆11Updated 10 years ago