xupsh / Amp-zynqLinks
Simple AMP Running Linux and Bare-Metal System on Both Zynq SoC Processors
☆22Updated 9 years ago
Alternatives and similar repositories for Amp-zynq
Users that are interested in Amp-zynq are comparing it to the libraries listed below
Sorting:
- Simple C snippet to transfer DMA memory with scatter/gather on a Zynq 7020☆54Updated 8 years ago
- ☆14Updated 8 years ago
- Example project that uses the AXI DMA peripheral to connect a custom AXI-Stream peripheral to memory☆13Updated 11 years ago
- This is a wiki and code sharing for ZYNQ☆72Updated 9 years ago
- FreeRTOS/lwIP (XAPP1026) for Xilinx Zynq devices using Vivado 2016.1. This port is compatible with Xilinx Vivado 2016.1 and was tested on…☆16Updated 8 years ago
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆33Updated 8 years ago
- Connecting FPGA and MCU using Ethernet RMII☆23Updated 9 years ago
- This repository contains a set of examples of opencl code that can run on the zedboard zynq all programmable soc.☆16Updated 9 years ago
- VHDL PCIe Transceiver☆28Updated 4 years ago
- ☆20Updated 3 weeks ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆34Updated 5 years ago
- ☆22Updated 8 years ago
- ☆17Updated last year
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆51Updated last year
- 本信号处理板主要由FPGA芯片和CYUSB3.0 芯片组成,其中FPGA模块主要完成与相关外设的交互,CYUSB3.0主要完成协议数据的传输。 2.2.1 FPGA模块 处理流程: 1. 链路初始化: 在上位机完成USB固件的下载,并读取…☆27Updated 9 years ago
- development interface mil-std-1553b for system on chip☆21Updated 7 years ago
- Verilog CAN controller that is compatible to the SJA 1000.☆13Updated 4 years ago
- Small footprint and configurable Inter-Chip communication cores☆59Updated 3 weeks ago
- ☆17Updated 4 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- iDEA FPGA Soft Processor☆16Updated 9 years ago
- LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G☆38Updated 2 years ago
- Open Hardware carrier board supporting modules with Zynq 7000 All Programmable SoC devices.☆58Updated last year
- Fork of OpenCores jpegencode with Cocotb testbench☆44Updated 9 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆66Updated last month
- Small footprint and configurable JESD204B core☆44Updated 3 weeks ago
- Open Source ZYNQ Board☆31Updated 9 years ago
- ☆19Updated 10 years ago
- Linux UIO Driver for AXI DMA☆14Updated 6 years ago
- an abstraction layer across user-space Linux, baremetal, and RTOS environments☆24Updated 3 weeks ago