xupgit / Basys3
XUP Basys3 Boards' LIBs and Projects
☆27Updated 7 years ago
Related projects ⓘ
Alternatives and complementary repositories for Basys3
- Extensible FPGA control platform☆54Updated last year
- Example design for the Ethernet FMC using the hard GEMs of the Zynq☆53Updated this week
- A set of Wishbone Controlled SPI Flash Controllers☆76Updated 2 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 4 years ago
- Basic floating-point components for RISC-V processors☆64Updated 4 years ago
- Wishbone interconnect utilities☆37Updated 5 months ago
- FuseSoC standard core library☆115Updated last month
- ☆63Updated 4 months ago
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆58Updated 4 years ago
- Verilog SPI master and slave☆46Updated 8 years ago
- turbo 8051☆28Updated 7 years ago
- A RISC-V processor☆13Updated 5 years ago
- A series of CORDIC related projects☆93Updated last week
- Open-source high performance AXI4-based HyperRAM memory controller☆58Updated 2 years ago
- I2C controller core☆33Updated last year
- SpinalHDL documentation assets (pictures, slides, ...)☆31Updated 3 weeks ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆123Updated 5 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 4 years ago
- SoftCPU/SoC engine-V☆54Updated last year
- RISCV model for Verilator/FPGA targets☆45Updated 5 years ago
- Mathematical Functions in Verilog☆85Updated 3 years ago
- JTAG Test Access Port (TAP)☆30Updated 10 years ago
- Small (Q)SPI flash memory programmer in Verilog☆55Updated 2 years ago
- Hamming ECC Encoder and Decoder to protect memories☆28Updated last month
- Verilog wishbone components☆109Updated 10 months ago
- A basic SpinalHDL project☆77Updated last month
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆92Updated 2 years ago
- An implementation of the CORDIC algorithm in Verilog.☆83Updated 6 years ago
- USB Full Speed PHY☆39Updated 4 years ago