Avnet / hdl
☆107Updated last week
Alternatives and similar repositories for hdl:
Users that are interested in hdl are comparing it to the libraries listed below
- Source code from the MicroZed Chronicles blog hosted by Xcell Daily Blog☆189Updated 6 years ago
- ☆54Updated 2 years ago
- (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…☆88Updated 6 years ago
- Demonstration of the AXI DMA engine on the ZedBoard☆51Updated 3 years ago
- This is a wiki and code sharing for ZYNQ☆71Updated 8 years ago
- Verilog digital signal processing components☆125Updated 2 years ago
- Example design for the Ethernet FMC using the hard GEMs of the Zynq☆54Updated 2 months ago
- Hardware, Linux Driver and Library for the Zynq AXI DMA interface☆100Updated 6 years ago
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆94Updated 2 years ago
- Raspberry Pi v2 camera (IMX219) to DisplayPort of Ultra96-V2 board through PL☆69Updated 2 years ago
- VHDL code for using Xilnx LVDS lines for MIPI CSI-2 TX protocol. For educational purposes☆62Updated last year
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆121Updated 4 years ago
- Avnet Board Definition Files☆129Updated 3 weeks ago
- A utility for Composing FPGA designs from Peripherals☆170Updated last month
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago
- ☆64Updated 6 months ago
- Repository used to support automated builds under PetaLinux tools that use Yocto.☆58Updated last week
- Example designs for FPGA Drive FMC☆231Updated 3 weeks ago
- Python tools for Vivado Projects☆73Updated 5 years ago
- ☆61Updated 7 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆61Updated 2 years ago
- ☆82Updated 7 years ago
- Extensible FPGA control platform☆56Updated last year
- Verilog modules required to get the OV7670 camera working☆65Updated 6 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆91Updated 4 years ago
- Fabric generator and CAD tools☆156Updated this week
- RTL Verilog library for various DSP modules☆84Updated 2 years ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆40Updated 6 years ago
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆149Updated 2 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆142Updated 2 years ago