imrickysu / ZYNQ-Custom-Board-Bring-Up-Guide
This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project that can help to investigate a bring-up problem.
☆64Updated 7 years ago
Related projects ⓘ
Alternatives and complementary repositories for ZYNQ-Custom-Board-Bring-Up-Guide
- Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard☆42Updated 2 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆87Updated 4 years ago
- Small footprint and configurable JESD204B core☆40Updated last month
- DPLL for phase-locking to 1PPS signal☆28Updated 8 years ago
- Extensible FPGA control platform☆54Updated last year
- A lightweight Controller Area Network (CAN) controller in VHDL☆24Updated 3 weeks ago
- This is a wiki and code sharing for ZYNQ☆71Updated 8 years ago
- JESD204b modules in VHDL☆29Updated 5 years ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆106Updated 3 years ago
- ☆40Updated 9 months ago
- JESD204B core for Migen/MiSoC☆36Updated 3 years ago
- ☆32Updated last year
- VHDL code for using Xilnx LVDS lines for MIPI CSI-2 TX protocol. For educational purposes☆60Updated last year
- Raspberry Pi v2 camera (IMX219) to DisplayPort of Ultra96-V2 board through PL☆67Updated 2 years ago
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆55Updated 2 years ago
- Capture images/video from a Raspberry Pi Camera (MIPI CSI-2) with an FPGA☆64Updated 4 years ago
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆41Updated 3 years ago
- Nitro USB FPGA core☆83Updated 8 months ago
- Open source AMD Xilinx Kria UltraScale+ SoM baseboard☆40Updated 2 months ago
- 🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)☆34Updated 3 years ago
- ☆106Updated this week
- Basic USB-CDC device core (Verilog)☆73Updated 3 years ago
- Dockerized FPGA toolchain experiments☆28Updated 9 months ago
- PYNQ-Z1 + AD936X openwifi capable SDR platform☆80Updated 2 years ago
- ☆16Updated 2 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆53Updated this week
- UART to AXI Stream interface written in VHDL☆16Updated 2 years ago
- ☆46Updated 3 years ago
- HDL code for a complex multiplier with AXI stream interface☆16Updated last year
- ☆22Updated 4 months ago