VoidMercy / Lattice-ECP5-Bitstream-Decompiler
Bitstream to Verilog decompiler for Lattice FPGA ECP5 chip.
☆20Updated 3 years ago
Alternatives and similar repositories for Lattice-ECP5-Bitstream-Decompiler:
Users that are interested in Lattice-ECP5-Bitstream-Decompiler are comparing it to the libraries listed below
- How to use the Intel JTAG primitive without using virtual JTAG☆16Updated 3 years ago
- Waveform Generator☆11Updated 2 years ago
- JTAG Hardware Abstraction Library☆36Updated last year
- Blink an LED on an FPGA in VHDL using ghdl, yosys and nextpnr☆26Updated 4 years ago
- Industry standard I/O for Amaranth HDL☆27Updated 3 months ago
- SPI flash MITM and emulation (QSPI is a WIP)☆20Updated 2 years ago
- The firmware, gateware, and host software of the ESP CPA Board.☆20Updated 8 months ago
- Drop In USB CDC ACM core for iCE40 FPGA☆33Updated 3 years ago
- A repo of basic Verilog/SystemVerilog modules useful in other circuits.☆21Updated 7 years ago
- An all-digital GPS disciplined oscillator using MMCM phase shift.☆27Updated 2 years ago
- An FPGA/PCI Device Reference Platform☆28Updated 4 years ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆15Updated 2 years ago
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆23Updated 3 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆37Updated 8 months ago
- Tool for decoding mask programmed PLAs from die shots☆21Updated 4 years ago
- ☆22Updated 2 years ago
- An MPEG2 video decoder, written in Verilog and implemented in an FPGA chip.☆22Updated 5 years ago
- LiteX LUNA USB stack integration☆14Updated 2 years ago
- Open source Logic Analyzer based on LiteX SoC☆24Updated 3 weeks ago
- 360nosc0pe Yocto build environment☆12Updated 6 years ago
- PCIe analyzer experiments☆49Updated 4 years ago
- Program to scan for malicious FPGA designs.☆13Updated 3 years ago
- SiLabs C8051F34x code protection bypass☆60Updated 3 years ago
- Easy-to-use JTAG TAP and Debug Controller core written in Verilog☆23Updated 6 years ago
- PCIe adapter for an FPGA accelerator for Open CloudServer☆22Updated 4 years ago
- VexRiscV system with GDB-Server in Hardware☆20Updated last year
- Interface for exposing raw NAND i/o over UART to enable pc-side modification.☆20Updated 6 years ago
- shdl6800: A 6800 processor written in SpinalHDL☆26Updated 5 years ago
- Container for compiling LiteX HDL FPGA designs using the free OpenXC7 tool chain and GitHub code spaces☆25Updated last year