RFID tag and tester in Verilog
☆42Apr 4, 2013Updated 13 years ago
Alternatives and similar repositories for rfid-verilog
Users that are interested in rfid-verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog library of EPC Gen-2 RFID Tag Baseband Processor for IC and FPGA designers☆41Dec 8, 2021Updated 4 years ago
- Verilog code for a low power RFID chip that will communicate with I2C sensors.☆13Apr 18, 2014Updated 12 years ago
- Implementation of Partially Parellel LDPC Code Decoder in Verilog☆15Jul 23, 2020Updated 6 years ago
- Zedboard projects☆11May 15, 2016Updated 10 years ago
- SERDES-based TDC core for Spartan-6☆19Aug 2, 2012Updated 13 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- RISC-V instruction set CPUs in HardCaml☆15Sep 20, 2016Updated 9 years ago
- 16QAM modulation and demodulation by Verilog☆20Jan 4, 2021Updated 5 years ago
- Open Agentic Design Automation - The open agent interface for EDA: Agent–EDA Contract☆17Updated this week
- MTI RFID Explorer is a software to help people to evaluate MTI UHF RFID modules and reader, including RU-861-XXX, RU-824-000 modules and …☆11Apr 10, 2019Updated 7 years ago
- Design and Verification of a Complete Application Specific Integrated Circuit☆12Nov 21, 2016Updated 9 years ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆15Jan 9, 2017Updated 9 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- discrete gate sizing☆14Nov 23, 2020Updated 5 years ago
- EPC C1G2 reader for the USRPv1☆27Dec 20, 2014Updated 11 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆14May 11, 2022Updated 4 years ago
- Initial 0.0.1 push☆13Jun 10, 2016Updated 10 years ago
- Partial Verilog implimentation of a WiMAX OFDM Phy☆19May 28, 2012Updated 14 years ago
- FFT algorithm coded in Verilog. Designed to run on a Xillinx Spartan 6 FPGA board.☆15Jul 19, 2012Updated 14 years ago
- Miscellaneous Experiments with LoRa☆12Sep 16, 2016Updated 9 years ago
- Port of Amber ARM Core project to Marsohod2 platform☆13Dec 4, 2019Updated 6 years ago
- HeiChips 2025 Tapeout on IHP SG13G2 130nm process☆23Apr 10, 2026Updated 3 months ago
- Moo CRFID☆19Feb 11, 2017Updated 9 years ago
- Library of generic verilog buildingblocks☆17Dec 25, 2025Updated 7 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Identifies ASL Hand Gesture for numbers using image processing in verilog☆15May 3, 2012Updated 14 years ago
- a fast multiplier implement using verilog☆13Dec 23, 2014Updated 11 years ago
- FPGA demo for Digilent NEXYS 4 board☆22Oct 2, 2019Updated 6 years ago
- This framework is featured to be handy but yet secured. This system use mobile communication device, which gives access to smart phones, …☆12May 19, 2018Updated 8 years ago
- ☆21Oct 28, 2024Updated last year
- Verilog Code for a JPEG Decoder☆34Mar 7, 2018Updated 8 years ago
- Implementation of RSA algorithm on FPGA using Verilog☆27Aug 1, 2018Updated 7 years ago
- Implementation of the SHA256 Algorithm in Verilog☆39Jan 2, 2012Updated 14 years ago
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆16Sep 28, 2017Updated 8 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Project 2.2 Frequency counter☆12May 30, 2025Updated last year
- Verilog Language Extension for Visual Studio☆20Jul 9, 2026Updated 2 weeks ago
- ☆18Jul 9, 2026Updated 2 weeks ago
- Standard cell placement (global and detailed) tool based on modified algorithm “simulated annealing”☆12Jan 7, 2026Updated 6 months ago
- Implementation of SHA256 Hasher with UART Transceiver in Verilog. Designed to run on Altera's DE2 FPGA Development Board.☆16Oct 16, 2018Updated 7 years ago
- a super-simple pipelined verilog divider. flexible to define stages☆61Jul 25, 2019Updated 7 years ago
- matrix-coprocessor for RISC-V☆36Feb 27, 2026Updated 4 months ago