Alternatives and similar repositories for rfid-verilog

Users that are interested in rfid-verilog are comparing it to the libraries listed below

• hukenovs / intfftk
  Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…
  ☆86Updated 2 years ago
• analogdevicesinc / fpgahdl_xilinx
  (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…
  ☆89Updated 7 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆114Updated last year
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆42Updated last year
• owocomm-0 / fpga-fft
  A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
  ☆125Updated 4 years ago
• m-labs / jesd204b
  JESD204B core for Migen/MiSoC
  ☆35Updated 4 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆49Updated 2 months ago
• GOOD-Stuff / FPGA-SPI-Flash
  Various projects of SPI loader module for xilinx fpga
  ☆33Updated 5 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆96Updated 5 years ago
• FPGAwars / FPGA-peripherals
  Collection of open-source peripherals in Verilog
  ☆183Updated 3 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆41Updated 7 years ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆30Updated 6 years ago
• dawsonjon / FPGA-radio
  Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC
  ☆111Updated 9 years ago
• siorpaes / BareBonesCortexM0
  Extremely basic CortexM0 SoC based on ARM DesignStart Eval
  ☆27Updated 7 years ago
• ZipCPU / interpolation
  Digital Interpolation Techniques Applied to Digital Signal Processing
  ☆67Updated last year
• coole198669 / viterbi_decoder
  Hardware Viterbi Decoder in verilog
  ☆28Updated 6 years ago
• russdill / bch_verilog
  Verilog based BCH encoder/decoder
  ☆129Updated 3 years ago
• ZipCPU / sdr
  A basic Soft(Gate)ware Defined Radio architecture
  ☆100Updated last year
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆41Updated 4 years ago
• thasti / fft
  synthesizable FFT IP block for FPGA designs
  ☆32Updated 6 years ago
• ZipCPU / cordic
  A series of CORDIC related projects
  ☆120Updated last year
• alexforencich / verilog-ft245
  Verilog FT245 to AXI stream interface
  ☆29Updated 7 years ago
• jfoshea / Viterbi-Decoder-in-Verilog
  An efficient implementation of the Viterbi decoding algorithm in Verilog
  ☆59Updated last year
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆48Updated 5 years ago
• ZipCPU / dspfilters
  A collection of demonstration digital filters
  ☆162Updated last year
• ZipCPU / fftdemo
  A demonstration showing how several components can be compsed to build a simulated spectrogram
  ☆47Updated last year
• forconesi / nfmac10g
  Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC
  ☆70Updated 8 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆84Updated 6 years ago
• fpgadeveloper / ethernet-fmc-zynq-gem
  Example design for the Ethernet FMC using the hard GEMs of the Zynq
  ☆60Updated 7 months ago