Alternatives and similar repositories for rfid-verilog:

Users that are interested in rfid-verilog are comparing it to the libraries listed below

• alexforencich / xfcp
  Extensible FPGA control platform
  ☆57Updated last year
• siorpaes / BareBonesCortexM0
  Extremely basic CortexM0 SoC based on ARM DesignStart Eval
  ☆24Updated 6 years ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆101Updated last year
• sbourdeauducq / serdes-tdc
  SERDES-based TDC core for Spartan-6
  ☆18Updated 12 years ago
• hukenovs / intfftk
  Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…
  ☆81Updated 2 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆46Updated last year
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆41Updated last month
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆29Updated 5 years ago
• owocomm-0 / fpga-fft
  A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
  ☆109Updated 4 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆32Updated 6 years ago
• fpga-soc / mil-std-1553b-soc
  development interface mil-std-1553b for system on chip
  ☆21Updated 7 years ago
• m-labs / jesd204b
  JESD204B core for Migen/MiSoC
  ☆36Updated 3 years ago
• rnz / verilog-sha256
  Implementation of the SHA256 Algorithm in Verilog
  ☆37Updated 13 years ago
• mcjtag / axis-uart
  AXI Stream UART (verilog)
  ☆11Updated 5 years ago
• Bucknalla / ip_cores
  Verilog IP Cores & Tests
  ☆13Updated 6 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆78Updated 5 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆42Updated 9 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆39Updated 4 years ago
• fpgadeveloper / ethernet-fmc-axi-eth
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆63Updated 3 months ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 6 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆29Updated 3 weeks ago
• poucotm / SublimeLinter-contrib-verilator
  👌 This linter plugin for SublimeLinter provides an interface to Verilator (Verilog Simulator)
  ☆15Updated 7 months ago
• ericgineer / CIC
  A CIC filter implemented in Verilog
  ☆22Updated 9 years ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆37Updated last year
• ultraembedded / core_ftdi_bridge
  FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge
  ☆32Updated 3 years ago
• myriadrf / LimeSDR-PCIe_GW
  Altera Cyclone IV FPGA project for the PCIe LimeSDR board
  ☆37Updated 2 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆35Updated 3 years ago
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆50Updated 9 years ago
• FPGA-Research / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆27Updated 3 years ago
• freecores / i2c
  I2C controller core
  ☆38Updated 2 years ago