Alternatives and similar repositories for FPGA-radio:

Users that are interested in FPGA-radio are comparing it to the libraries listed below

• owocomm-0 / fpga-fft
  A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
  ☆108Updated 3 years ago
• alberto-grl / 1bitSDR
  Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom
  ☆102Updated 4 years ago
• ZipCPU / sdr
  A basic Soft(Gate)ware Defined Radio architecture
  ☆76Updated last year
• LukiLeu / FPGA_ADC
  An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components
  ☆42Updated 3 years ago
• emard / flearadio
  Digital FM Radio Receiver for FPGA
  ☆60Updated 9 years ago
• dawsonjon / FPGA-TX
  FPGA based transmitter
  ☆91Updated 7 years ago
• regymm / PYNQSDR
  PYNQ-Z1 + AD936X openwifi capable SDR platform
  ☆81Updated 2 years ago
• daveshah1 / RFToolSDR
  AD9361 based USB3 SDR
  ☆100Updated 7 years ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆100Updated last year
• hamsternz / second_order_sigma_delta_DAC
  A comparison of 1st and 2nd order sigma delta DAC for FPGA
  ☆55Updated 4 years ago
• efard / DSPHDL
  ☆40Updated 10 months ago
• DiegoRosales / VHDL_Modules
  VHDL Modules
  ☆23Updated 9 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆55Updated last year
• ZipCPU / dspfilters
  A collection of demonstration digital filters
  ☆142Updated last year
• mattvenn / fpga-sdft
  sliding DFT for FPGA, targetting Lattice ICE40 1k
  ☆73Updated 4 years ago
• ZipCPU / fftdemo
  A demonstration showing how several components can be compsed to build a simulated spectrogram
  ☆40Updated 9 months ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆86Updated 4 years ago
• esynr3z / proto245
  🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)
  ☆35Updated 3 years ago
• MorrisMA / 1PPS-DPLL
  DPLL for phase-locking to 1PPS signal
  ☆28Updated 8 years ago
• ZipCPU / dblclockfft
  A configurable C++ generator of pipelined Verilog FFT cores
  ☆227Updated 9 months ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆120Updated 2 years ago
• yrrapt / amsat_txrx_ic
  An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)
  ☆70Updated 3 years ago
• davemuscle / sigma_delta_converters
  Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components
  ☆59Updated 2 years ago
• amaranth-farm / amlib
  assorted library of utility cores for amaranth HDL
  ☆85Updated 4 months ago
• ZipCPU / interpolation
  Digital Interpolation Techniques Applied to Digital Signal Processing
  ☆56Updated 6 months ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 6 years ago
• OpenResearchInstitute / dvb_fpga
  RTL implementation of components for DVB-S2
  ☆112Updated last year
• m-labs / jesd204b
  JESD204B core for Migen/MiSoC
  ☆36Updated 3 years ago
• hukenovs / intfftk
  Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…
  ☆79Updated last year
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆54Updated this week