Alternatives and similar repositories for microbench

Users that are interested in microbench are comparing it to the libraries listed below

• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆75Updated 5 years ago
• ppeetteerrs / gem5-RISC-V-FS-Linux
  Repository containing the guide and code for booting RISC-V full system linux using gem5.
  ☆56Updated 4 years ago
• esl-epfl / gem5-X
  The gem5-X open source framework (based on the gem5 simulator)
  ☆42Updated 2 years ago
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆127Updated last year
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆33Updated 2 years ago
• gem5bootcamp / gem5-bootcamp-env
  The gem5 Bootcamp 2022 environment. Archived.
  ☆36Updated last year
• arm-university / arm-gem5-rsk
  Official repository of the Arm Research Starter Kit on System Modeling using gem5
  ☆118Updated 7 months ago
• riscv-stc / riscv-matrix-spec
  RISC-V Matrix Specification
  ☆23Updated last year
• SingularityKChen / SystemC-Training
  SystemC training aimed at TLM.
  ☆35Updated 5 years ago
• eric-rotenberg / CVP
  Championship Value Prediction (CVP) simulator.
  ☆17Updated 4 years ago
• TeCSAR-UNCC / gem5-SALAM
  ☆109Updated last year
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆114Updated 2 years ago
• Arteris-IP / tlm2-interfaces
  contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
  ☆63Updated 3 weeks ago
• OpenXiangShan / GEM5
  ☆125Updated this week
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆73Updated last year
• gem5 / gem5-resources
  The official repository for the gem5 resources sources.
  ☆80Updated 3 weeks ago
• zslwyuan / PAAS_V1.0
  PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
  ☆43Updated 4 years ago
• sparcians / map
  Modeling Architectural Platform
  ☆216Updated this week
• ucb-bar / sha3
  ☆82Updated last year
• ccelio / Speckle
  A wrapper for the SPEC CPU2006 benchmark suite.
  ☆91Updated 4 years ago
• Jerc007 / Open-GPGPU-FlexGrip-
  FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
  ☆118Updated 2 years ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆62Updated 4 years ago
• UT-LCA / Scalability-Phase-Simpoint-of-SPEC-CPU2017
  ☆33Updated 5 years ago
• riscv-boom / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆40Updated 6 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆109Updated 4 years ago
• ucb-bar / virgo
  Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC
  ☆46Updated 2 weeks ago
• tukl-msd / gem5.TnT
  gem5 Tips & Tricks
  ☆71Updated 5 years ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆111Updated 4 months ago
• tukl-msd / DRAMPower
  Fast and accurate DRAM power and energy estimation tool
  ☆189Updated this week
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆100Updated 2 months ago