WangXuan95 / USTC-RVSoCView on GitHub
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC,包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
433Sep 14, 2023Updated 2 years ago

Alternatives and similar repositories for USTC-RVSoC

Users that are interested in USTC-RVSoC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.

Sorting:

Are these results useful?