WangXuan95 / USTC-RVSoCView on GitHub
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC,包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
429Sep 14, 2023Updated 2 years ago

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