vanDeagle / Traffic-sign-recongnition-on-PYNQ-Z2
☆14Updated 4 years ago
Alternatives and similar repositories for Traffic-sign-recongnition-on-PYNQ-Z2:
Users that are interested in Traffic-sign-recongnition-on-PYNQ-Z2 are comparing it to the libraries listed below
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆135Updated last year
- ☆50Updated last year
- hls code zynq 7020 pynq z2 CNN☆79Updated 5 years ago
- ☆205Updated 9 months ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆132Updated 2 months ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- 搭建卷积神经网络并利用FPGA加速实现交通标志识别☆26Updated 4 years ago
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的,只有主干网络部署在fpga上,片上资源无法支持整个网络所需资源,建议添加外部存储及DDR☆73Updated last year
- 中文:☆94Updated 5 years ago
- 【入门项目】这个仓库是用hls来实现手写数字识别CNN硬件(xilinx fpga)加速的代码☆69Updated 2 years ago
- PYNQ学习资料☆160Updated 5 years ago
- Lenet for MNIST handwritten digit recognition using Vivado hls tool☆36Updated 4 years ago
- FPGA/AES/LeNet/VGG16☆93Updated 6 years ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆68Updated 6 years ago
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆194Updated last year
- Convolutional Neural Network Using High Level Synthesis☆84Updated 4 years ago
- An LeNet RTL implement onto FPGA☆40Updated 6 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆163Updated 10 months ago
- ☆59Updated 2 years ago
- FPGA☆144Updated 7 months ago
- MNIST using tensorflow, c++ and fpga (zynq7010)☆26Updated last year
- Implementation of YOLOv3-tiny + Depthwise Separable Convolution on FPGA☆27Updated 2 years ago
- This project will use ZYNQ 7020 to build the PYNQ framework, and build face detection algorithm, and finally use USB camera to detect fac…☆24Updated 3 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆15Updated 6 years ago
- Pynq computer vision examples with an OV5640 camera☆44Updated 4 years ago
- The CNN based on the Xilinx Vivado HLS☆37Updated 3 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆175Updated last year
- verilog实现TPU中的脉动阵列计算卷积的module☆73Updated 3 years ago
- A simple demo to implement the Handwritten Mathematical Calculator on PYNQ-Z2 FPGA platform by using HLS.☆37Updated 4 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆61Updated 6 years ago