High-performance FPGA-based JPEG codec accelerator
☆13Dec 1, 2018Updated 7 years ago
Alternatives and similar repositories for FPGA-based-JPEG-codec-accelerator
Users that are interested in FPGA-based-JPEG-codec-accelerator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.☆18Aug 31, 2020Updated 6 years ago
- - Use FPGA to implement MIPI interface; - Get command from PC through USB communication; - Decode command in FPGA☆13Jul 18, 2017Updated 9 years ago
- JPEG2000 compression coder on Xilinx Virtex 5 FPGA☆20Jul 17, 2013Updated 13 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆40Oct 25, 2020Updated 6 years ago
- A hardware MJPEG encoder and RTP transmitter☆49Jan 15, 2020Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- An MPEG2 video decoder, written in Verilog and implemented in an FPGA chip.☆27Apr 24, 2019Updated 7 years ago
- A simple JPEG2000 hardware encoder☆29Sep 29, 2020Updated 6 years ago
- ☆25Dec 31, 2022Updated 3 years ago
- This repository includes some FPGA projects like VGA control, image processing. So far, fpga can drive a VGA monitor and display an image…☆14Jul 5, 2017Updated 9 years ago
- Verilog Code for a JPEG Decoder☆34Mar 7, 2018Updated 8 years ago
- Video compression systems☆24Jul 17, 2014Updated 12 years ago
- FPGA PWM generator and motor controller modules☆12Mar 9, 2021Updated 5 years ago
- OV7670 (Verilog HDL)Drive for FPGA☆19Mar 4, 2019Updated 7 years ago
- NoC based MPSoC☆11Jul 17, 2014Updated 12 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- 基于FPGA的FFT算法并行优化☆13Mar 7, 2024Updated 2 years ago
- This is the repository for a verilog implementation of a lzrw1 compression core☆20Dec 8, 2017Updated 8 years ago
- Example design for the Ethernet FMC using an FPGA based hardware packet generator/checker to demonstrate maximum throughput☆12Oct 12, 2026Updated 3 weeks ago
- STM32F103C8T6_CUBEMX_TRUESTUDIO_XINPUT_JOYSTICK☆10Jun 5, 2017Updated 9 years ago
- 基于FPGA的FFT☆19Feb 18, 2019Updated 7 years ago
- An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码…☆347Sep 18, 2024Updated 2 years ago
- 基于FPGA的PCIe 板卡，支持 离散量输入输出、ARINC429协议☆18Dec 1, 2022Updated 3 years ago
- Hardware random number generator for FPGAs☆10May 7, 2015Updated 11 years ago
- Verilog code to connect the HC-SR04 ultrasonic sensor to the DE10-Lite fpga board☆11Apr 18, 2018Updated 8 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Tensor Processing Unit implementation in Verilog☆16Aug 12, 2026Updated 2 months ago
- An oscilloscope written for the Mojo V3, a Spartan-6 based FPGA☆11May 23, 2017Updated 9 years ago
- The BT656_out module is a configurable BT.656 video encoder that supports both 8-bit and 10-bit video output formats. This implementation…☆16Jan 6, 2026Updated 9 months ago
- RISC-V OpenWrt Port☆17Oct 30, 2018Updated 8 years ago
- Nexys 4 DDR Artix-7☆12Jun 15, 2018Updated 8 years ago
- fpga for utrasound mobile device☆13Aug 10, 2015Updated 11 years ago
- ☆15Aug 1, 2023Updated 3 years ago
- 七路图像在FPGA中实现拼接，代码会不断添加进来。☆30Aug 17, 2021Updated 5 years ago
- MTCNN with convolution reprogramed in c☆14Jul 25, 2019Updated 7 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- digital recognition base on FPGA☆12Nov 10, 2019Updated 6 years ago
- maskcnn_benchmark based on mobilenetv2☆12Nov 11, 2019Updated 6 years ago
- High throughput JPEG decoder in Verilog for FPGA☆283Mar 5, 2022Updated 4 years ago
- A Voila-Jones face detector hardware implementation☆33Nov 29, 2018Updated 7 years ago
- TCL framework to package Vivado IP-Cores☆13May 18, 2022Updated 4 years ago
- Digital Logic Lecture Final Project in the first term of year 2020-21☆11Jan 25, 2021Updated 5 years ago
- FPGA-Based USB-Input Audio Digital to Analogue Converter☆18Jun 11, 2021Updated 5 years ago