Alternatives and similar repositories for quickfeather-notes:

Users that are interested in quickfeather-notes are comparing it to the libraries listed below

• mattvenn / vga_clock_pcb
  Open source hardware down to the chip level!
  ☆30Updated 3 years ago
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆32Updated 3 years ago
• amaranth-lang / amaranth-stdio
  Industry standard I/O for Amaranth HDL
  ☆28Updated 6 months ago
• pepijndevos / seqpu
  A bit-serial CPU
  ☆18Updated 5 years ago
• m-labs / microscope
  Finding the bacteria in rotting FPGA designs.
  ☆14Updated 4 years ago
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆21Updated 3 years ago
• mmicko / cross-fpga
  Cross compile FPGA tools
  ☆22Updated 4 years ago
• xobs / spibone
  Wishbone bridge over SPI
  ☆11Updated 5 years ago
• icebreaker-fpga / icebreaker-amaranth-examples
  This repository contains iCEBreaker examples for Amaranth HDL.
  ☆38Updated last year
• hamsternz / lfsr_scramblers
  Experiments with self-synchronizing LFSR scramblers
  ☆15Updated 4 years ago
• litex-hub / litehyperbus
  Small footprint and configurable HyperBus core
  ☆11Updated 2 years ago
• xobs / lxbuildenv
  Simplified environment for litex
  ☆14Updated 4 years ago
• whitequark / icefloorplan
  iCE40 floorplan viewer
  ☆24Updated 6 years ago
• YosysHQ / prjtrellis-db
  Project Trellis database
  ☆13Updated last year
• awygle / waggle
  Rust proof-of-concept for GPU waveform rendering
  ☆13Updated 4 years ago
• tomverbeure / sidechan
  Side channel communication test within an FPGA
  ☆11Updated 4 years ago
• umarcor / SIEAV
  Co-simulation and behavioural verification with VHDL, C/C++ and Python/m
  ☆13Updated last week
• m-labs / nmigen-soc
  System on Chip toolkit for nMigen
  ☆19Updated 5 years ago
• gatecat / hrt
  Hot Reconfiguration Technology demo
  ☆39Updated 2 years ago
• OpenCAPI / omi_device_ice
  An example OMI Device FPGA with 2 DDR4 memory ports
  ☆16Updated 2 years ago
• ulixxe / usb_dfu
  Full Speed USB DFU interface for FPGA and ASIC designs
  ☆17Updated last year
• xobs / valentyusb
  USB Full-Speed core written in migen/LiteX
  ☆12Updated 5 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆57Updated 2 weeks ago
• ECP5-PCIe / ECP5-Utils
  Utilities for the ECP5 FPGA
  ☆18Updated 3 years ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆48Updated 3 months ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• jeanthom / gram
  DDR3 controller for nMigen (WIP)
  ☆14Updated last year
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 2 years ago
• YosysHQ / prjpeppercorn
  Project Peppercorn - GateMate FPGA Bitstream Documentation
  ☆18Updated last week
• prjunnamed / prjcombine
  An FPGA reverse engineering and documentation project
  ☆43Updated this week