Alternatives and similar repositories for digitaljs

Users that are interested in digitaljs are comparing it to the libraries listed below

• tilk / digitaljs_online
  Online demonstration for DigitalJS
  ☆136Updated last year
• nturley / netlistsvg
  draws an SVG schematic from a JSON netlist
  ☆709Updated last year
• sylefeb / Silice
  Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pi…
  ☆1,371Updated 3 weeks ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,420Updated 4 months ago
• hdl-util / hdmi
  Send video/audio over HDMI on an FPGA
  ☆1,173Updated last year
• tinyvision-ai-inc / UPduino-v3.0
  UPduino 3.0: new 4 layer layout, various other improvements
  ☆337Updated 5 months ago
• drom / awesome-hdl
  Hardware Description Languages
  ☆1,038Updated 4 months ago
• dawsonjon / Chips-2.0
  FPGA Design Suite based on C to Verilog design flow.
  ☆244Updated 6 years ago
• rsd-devel / rsd
  RSD: RISC-V Out-of-Order Superscalar Processor
  ☆1,087Updated 3 months ago
• kelu124 / awesome-latticeFPGAs
  List of FPGA Lattice boards using open tools
  ☆326Updated this week
• FPGAwars / icestudio
  Visual editor for open FPGA boards
  ☆1,785Updated 2 weeks ago
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆1,038Updated this week
• vmware-archive / cascade
  A Just-In-Time Compiler for Verilog from VMware Research
  ☆445Updated 3 years ago
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,459Updated this week
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆335Updated last month
• siliconcompiler / logik
  A configurable RTL to bitstream FPGA toolchain
  ☆35Updated this week
• m-labs / nmigen
  A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
  ☆672Updated 3 years ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆305Updated last year
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,349Updated this week
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆696Updated last week
• Domipheus / RPU
  Basic RISC-V CPU implementation in VHDL.
  ☆166Updated 4 years ago
• MoonbaseOtago / vroom
  VRoom! RISC-V CPU
  ☆505Updated 9 months ago
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆370Updated last year
• RTimothyEdwards / magic
  Magic VLSI Layout Tool
  ☆543Updated last week
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,300Updated last week
• wavedrom / bitfield
  bit field diagram renderer
  ☆366Updated last year
• m-labs / migen
  A Python toolbox for building complex digital hardware
  ☆1,282Updated 2 weeks ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆884Updated 2 years ago
• andrescv / jupiter
  RISC-V Assembler and Runtime Simulator
  ☆431Updated last year
• YosysHQ / fpga-toolchain
  Multi-platform nightly builds of open source FPGA tools
  ☆296Updated 3 years ago