google / CFU-Playground
Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.github.io/CFU-Playground/ For reference docs, see the link below.
☆470Updated this week
Related projects ⓘ
Alternatives and complementary repositories for CFU-Playground
- A open source reimplementation of Google's Tensor Processing Unit (TPU).☆364Updated 6 years ago
- Modular hardware build system☆861Updated this week
- Berkeley's Spatial Array Generator☆811Updated this week
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆150Updated 2 months ago
- Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.☆295Updated last week
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆387Updated 2 months ago
- A Linux-capable RISC-V multicore for and by the world☆622Updated this week
- Open source machine learning accelerators☆358Updated 7 months ago
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆884Updated this week
- An open-source static random access memory (SRAM) compiler.☆832Updated 4 months ago
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆248Updated 3 weeks ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆338Updated this week
- FOSS Flow For FPGA☆360Updated 3 weeks ago
- RISC-V Debug Support for our PULP RISC-V Cores☆224Updated this week
- CORE-V Family of RISC-V Cores☆206Updated 8 months ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆371Updated this week
- FuseSoC-based SoC for VeeR EH1 and EL2☆290Updated 2 months ago
- Example designs showing different ways to use F4PGA toolchains.☆265Updated 7 months ago
- The OpenPiton Platform☆643Updated last month
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆433Updated 2 weeks ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆218Updated 11 months ago
- An abstraction library for interfacing EDA tools☆637Updated last week
- OpenSource GPU, in Verilog, loosely based on RISC-V ISA☆820Updated 4 months ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆266Updated this week
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆260Updated last week
- A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …☆599Updated last week
- Vitis HLS LLVM source code and examples☆379Updated last month
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆452Updated 6 months ago
- A 256-RISC-V-core system with low-latency access into shared L1 memory.☆275Updated this week
- VeeR EL2 Core☆252Updated this week