Alternatives and similar repositories for CFU-Playground

Users that are interested in CFU-Playground are comparing it to the libraries listed below

• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆401Updated 3 months ago
• tensil-ai / tensil
  Open source machine learning accelerators
  ☆397Updated last year
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆1,127Updated this week
• ucb-bar / gemmini
  Berkeley's Spatial Array Generator
  ☆1,215Updated this week
• UCSBarchlab / OpenTPU
  A open source reimplementation of Google's Tensor Processing Unit (TPU).
  ☆731Updated 8 years ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆539Updated last year
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆377Updated 11 months ago
• pymtl / pymtl3
  Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
  ☆445Updated 5 months ago
• jofrfu / tinyTPU
  Implementation of a Tensor Processing Unit for embedded systems and the IoT.
  ☆541Updated 7 years ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆568Updated 3 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆334Updated last year
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆324Updated 11 months ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆485Updated 2 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆316Updated last month
• danielholanda / LeFlow
  Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks
  ☆622Updated 6 years ago
• ztachip / ztachip
  Opensource software/hardware platform to build edge AI solutions deployed on FPGA or custom ASIC hardware.
  ☆287Updated last week
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆1,000Updated 3 weeks ago
• Xilinx / HLS
  Vitis HLS LLVM source code and examples
  ☆403Updated 4 months ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆766Updated 4 months ago
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆226Updated 3 weeks ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆759Updated this week
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆292Updated this week
• os-fpga / open-source-fpga-resource
  A list of resources related to the open-source FPGA projects
  ☆439Updated 3 years ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆317Updated this week
• KastnerRG / pp4fpgas
  Parallel Programming for FPGAs -- An open-source high-level synthesis book
  ☆875Updated 3 weeks ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆457Updated 8 months ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆305Updated 2 years ago
• hughperkins / VeriGPU
  OpenSource GPU, in Verilog, loosely based on RISC-V ISA
  ☆1,239Updated last year
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆293Updated 3 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆641Updated 3 weeks ago