Alternatives and similar repositories for CFU-Playground

Users that are interested in CFU-Playground are comparing it to the libraries listed below

• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆384Updated 3 months ago
• UCSBarchlab / OpenTPU
  A open source reimplementation of Google's Tensor Processing Unit (TPU).
  ☆706Updated 7 years ago
• tensil-ai / tensil
  Open source machine learning accelerators
  ☆387Updated last year
• jofrfu / tinyTPU
  Implementation of a Tensor Processing Unit for embedded systems and the IoT.
  ☆508Updated 6 years ago
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆1,091Updated this week
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆353Updated 7 months ago
• pymtl / pymtl3
  Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
  ☆430Updated last month
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆301Updated 7 months ago
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆180Updated this week
• Xilinx / HLS
  Vitis HLS LLVM source code and examples
  ☆396Updated last week
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆739Updated this week
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆326Updated 10 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆531Updated last month
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆274Updated 2 weeks ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆463Updated 2 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆297Updated this week
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆515Updated 10 months ago
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆420Updated this week
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆219Updated 4 months ago
• firesim / firesim
  FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
  ☆968Updated 3 months ago
• ztachip / ztachip
  Opensource software/hardware platform to build edge AI solutions deployed on FPGA or custom ASIC hardware.
  ☆270Updated 6 months ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆731Updated 2 weeks ago
• ucb-bar / gemmini
  Berkeley's Spatial Array Generator
  ☆1,066Updated last month
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆612Updated this week
• hughperkins / VeriGPU
  OpenSource GPU, in Verilog, loosely based on RISC-V ISA
  ☆1,093Updated 10 months ago
• os-fpga / open-source-fpga-resource
  A list of resources related to the open-source FPGA projects
  ☆424Updated 2 years ago
• chipsalliance / Cores-VeeR-EH2
  ☆245Updated 2 years ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆407Updated 9 months ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆899Updated 2 years ago
• ben-marshall / awesome-open-hardware-verification
  A List of Free and Open Source Hardware Verification Tools and Frameworks
  ☆560Updated 2 years ago