Simple UART controller for FPGA written in VHDL
☆110Aug 7, 2021Updated 5 years ago
Alternatives and similar repositories for uart-for-fpga
Users that are interested in uart-for-fpga are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SPI master and SPI slave for FPGA written in VHDL☆185Apr 24, 2021Updated 5 years ago
- ☆23Oct 20, 2023Updated 2 years ago
- RMII Firewall FPGA☆25Dec 2, 2019Updated 6 years ago
- BEBA Software Switch implementation☆14Jul 28, 2017Updated 9 years ago
- Xilinx Platform cable USB and impact on linux without windrvr by Michael Gernoth☆14Apr 17, 2014Updated 12 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated 5 months ago
- Python 3 drivers for HDC1080/HDC1000 for the Raspberry Pi☆10Dec 16, 2018Updated 7 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆13Aug 26, 2023Updated 3 years ago
- A FPGA core for a simple SDRAM controller.☆126Nov 13, 2021Updated 4 years ago
- Sketches for DesignLab☆16Sep 10, 2017Updated 8 years ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆219Jul 27, 2026Updated last month
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆22May 4, 2017Updated 9 years ago
- Tcl examples repository designed primarily for use with the latest version of the Libero® SoC Design Suite.☆11Jul 18, 2024Updated 2 years ago
- A VHDL UART for communicating over a serial link with an FPGA☆87Mar 1, 2016Updated 10 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- An unofficial LaTeX Beamer theme that is trying to follow the Coprorate Design Guidelines of Leibniz Universität Hannover.☆18Mar 28, 2025Updated last year
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Apr 20, 2014Updated 12 years ago
- Transfer waveforms from Tektronix Oscilloscopes using the High-Speed Interface☆12Updated this week
- Amiga 600 with Gayle 1: VHDL implementation of PAL16L8B (XU1) with Lattice GAL16V8☆13Jul 31, 2018Updated 8 years ago
- ☆14Jan 22, 2026Updated 7 months ago
- [Course] Hands-On ZYNQ: Mastering AXI4 Bus Protocol☆19Feb 22, 2020Updated 6 years ago
- ☆48May 18, 2016Updated 10 years ago
- C64 core☆14Jul 25, 2026Updated last month
- FPGA design toolkit with templates and standard modules☆27May 31, 2026Updated 2 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- ESnet general-purpose FPGA design library.☆14Updated this week
- Notes on the Eclypse Z7 development board☆17Apr 9, 2026Updated 4 months ago
- VHDL 1802 Core with TinyBASIC for the Lattice MachXO2 Pico board☆16Dec 23, 2016Updated 9 years ago
- ☆26Feb 8, 2022Updated 4 years ago
- 1G eth UDP / IP Stack☆10Jul 17, 2014Updated 12 years ago
- IP cores for the FPGA Libre project☆12Aug 7, 2017Updated 9 years ago
- ☆25May 3, 2020Updated 6 years ago
- Verilog SDR SDRAM controller for FPGA Xilinx and Lattice☆17Jan 3, 2021Updated 5 years ago
- Simple SoC in VHDL with full toolchain and custom board.☆28Jun 4, 2018Updated 8 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆10Jan 26, 2023Updated 3 years ago
- Library of VHDL components that are useful in larger designs.☆246Oct 10, 2023Updated 2 years ago
- Create database files for the genealogytree LaTeX package from GEDCOM files☆11May 21, 2026Updated 3 months ago
- ☆18Jul 28, 2022Updated 4 years ago
- An interactive digital logic simulator with verilog support (Yosys)☆28Apr 2, 2026Updated 4 months ago
- The developed solution for designing an affordable manipulator to be used for teaching proposes where students get to use an FPGA and the…☆11Oct 3, 2023Updated 2 years ago
- Library for reading Xilinx .bit bitstream file headers with metadata extraction☆14Apr 7, 2026Updated 4 months ago