Alternatives and similar repositories for zynq-sandbox

Users that are interested in zynq-sandbox are comparing it to the libraries listed below

• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆96Updated 2 years ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆33Updated 10 months ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆60Updated 2 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆78Updated 4 years ago
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆17Updated 5 years ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆178Updated 4 months ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆44Updated 9 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆62Updated this week
• benreynwar / pyvivado
  Python tools for Vivado Projects
  ☆73Updated 6 years ago
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆37Updated 5 years ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago
• unihd-cag / openhmc
  openHMC - an open source Hybrid Memory Cube Controller
  ☆48Updated 9 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆41Updated last year
• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆55Updated 7 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆93Updated 7 months ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 3 months ago
• jbush001 / PASC
  Parallel Array of Simple Cores. Multicore processor.
  ☆99Updated 6 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• forconesi / nfmac10g
  Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC
  ☆62Updated 8 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆80Updated last week
• plex1 / SpinalDev
  Docker Development Environment for SpinalHDL
  ☆20Updated 9 months ago
• laforest / Octavo
  Verilog FPGA Parts Library. Old Octavo soft-CPU project.
  ☆74Updated 6 years ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 2 years ago
• benjmarshall / hlsclt
  A Vivado HLS Command Line Helper Tool
  ☆36Updated 3 years ago
• pieter3d / simview
  ☆78Updated last year
• rajesh-s / axi_cheatsheet
  A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)
  ☆27Updated 6 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 2 years ago