Alternatives and similar repositories for boost-edif-parser

Users that are interested in boost-edif-parser are comparing it to the libraries listed below

• chiphackers / ModelNetlist
  This repository contains a simple model for representing netlist (electronics) in python
  ☆9Updated 7 months ago
• FPGA-Research / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆30Updated 4 years ago
• paripath / cdf
  Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format
  ☆12Updated 5 years ago
• The-OpenROAD-Project-Attic / ioPlacer
  IO and Pin Placer for Floorplan-Placement Subflow
  ☆22Updated 4 years ago
• skuep / GDS3D
  Fork from https://sourceforge.net/projects/gds3d
  ☆68Updated last year
• ashtanyuk / GDSII-Links
  GDSII file format links
  ☆13Updated 5 years ago
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆40Updated last year
• eda-ricercatore / Modica-SRAM
  Design of a 32-kbit synchronous SRAM with 32-bit words, using 180 nm process technology. Developed MATLAB scripts to evaluate architectu…
  ☆15Updated 4 years ago
• parallella / openeda
  Open source EDA chip design flow
  ☆51Updated 8 years ago
• levibyte / channel_router
  demo on simple channel router
  ☆13Updated 6 years ago
• verilog-to-routing / tatum
  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
  ☆62Updated last year
• The-OpenROAD-Project / ORAssistant
  OpenROAD's Chatbot Assistant
  ☆19Updated this week
• Rishabh-zhcet / Analog-to-Digital-Converter
  This repository presents the mixed signal design of a Counter Type/ Ramp Type ADC. The Digital part of the circuit i.e 4- bit counter is …
  ☆9Updated 3 years ago
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• ahmed-agiza / EDAViewer
  EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
  ☆72Updated 2 years ago
• The-OpenROAD-Project / PcbRouter
  ☆31Updated 4 years ago
• rachelselinar / ReGDS-Logic-Gate-Extraction
  A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog …
  ☆30Updated 10 months ago
• os-fpga / FOEDAG
  Framework Open EDA Gui
  ☆68Updated 7 months ago
• purdue-onchip / gds2Para
  GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
  ☆119Updated 2 years ago
• ucdrstdenis / cdsAsync
  cdsAsync: An Asynchronous QDI VLSI Toolset & Schematic Library
  ☆25Updated this week
• mgraczyk / coursera-vlsicad
  Programming assignments for Coursera's U of I VLSI CAD: Logic to Layout
  ☆12Updated 11 years ago
• litaotju / edif-parser
  A c project for EDIF format parse.
  ☆13Updated 9 years ago
• The-OpenROAD-Project / OpenDP
  Open Source Detailed Placement engine
  ☆11Updated 5 years ago
• SymbiFlow / vtr-verilog-to-routing
  SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆38Updated 10 months ago
• AmiArnab / Synopsys
  Basic scripts for Synopsys Design Compiler and Synopsys IC Compiler
  ☆10Updated 7 years ago
• ganeshgore / spydrnet-physical
  This is a SpyDrNet Plugin for a physical design related transformations
  ☆13Updated last month
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆56Updated 4 years ago
• The-OpenROAD-Project / asap7_pdk_r1p7
  ☆19Updated last year
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆93Updated 3 years ago
• s-holst / GDS2WebGL
  Translates GDSII into HTML/JS that can be viewed in WebGL-capable web browsers.
  ☆55Updated 4 years ago