Alternatives and similar repositories for boost-edif-parser:

Users that are interested in boost-edif-parser are comparing it to the libraries listed below

• FPGA-Research / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆27Updated 3 years ago
• verilog-to-routing / tatum
  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
  ☆56Updated 7 months ago
• aolofsson / POSH
  ☆40Updated 4 years ago
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆55Updated 3 months ago
• parallella / openeda
  Open source EDA chip design flow
  ☆49Updated 7 years ago
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆86Updated 2 years ago
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆34Updated 11 months ago
• os-fpga / FOEDAG
  Framework Open EDA Gui
  ☆63Updated last month
• ganeshgore / spydrnet-physical
  This is a SpyDrNet Plugin for a physical design related transformations
  ☆11Updated this week
• limerainne / Dockerize-EDA
  [WIP] Dockerize Synopsys/Cadence EDA tools
  ☆82Updated 5 years ago
• EECS150 / asic_labs_fa21
  ☆20Updated 3 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆62Updated 4 years ago
• bluecheetah / bag
  BAG framework
  ☆40Updated 5 months ago
• ahmed-agiza / EDAViewer
  EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
  ☆69Updated 2 years ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆46Updated 8 months ago
• The-OpenROAD-Project-Attic / ioPlacer
  IO and Pin Placer for Floorplan-Placement Subflow
  ☆22Updated 4 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 9 years ago
• idea-fasoc / fasoc
  ☆53Updated last year
• daitoto / EDA-wiki
  EDA wiki
  ☆51Updated last year
• bhunt2 / DDR4Sim
  DDR4 Simulation Project in System Verilog
  ☆32Updated 10 years ago
• torc-isi / torc
  Torc: Tools for Open Reconfigurable Computing
  ☆39Updated 7 years ago
• x-epic / EpicSim
  EpicSim Project
  ☆70Updated 3 years ago
• fredrequin / verilator_xilinx
  Re-coded Xilinx primitives for Verilator use
  ☆41Updated 10 months ago
• Mario-Hero / Async-Karin
  Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-…
  ☆29Updated 4 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆57Updated 2 months ago
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆28Updated 3 years ago
• skuep / GDS3D
  Fork from https://sourceforge.net/projects/gds3d
  ☆67Updated 7 months ago
• The-OpenROAD-Project / SA-PCB
  Annealing-based PCB placement tool
  ☆35Updated 4 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• The-OpenROAD-Project / OpenDP
  Open Source Detailed Placement engine
  ☆11Updated 4 years ago