uoyniXnaH / AXL-SKILL

Related projects ⓘ

Alternatives and complementary repositories for AXL-SKILL

• lukeli17 / Allegro_Skill_ziliao
  Cadence Skill资料收集
  ☆18Updated 2 years ago
• FEDEVEL / allegro-script-add_layer_name
  ☆19Updated 7 years ago
• lukeli17 / Allegro_Skill_LY
  收集Cadence一些实用的Skill（自用）
  ☆12Updated 2 years ago
• whh5118 / GTOpen
  几楼科技 Cadence Allegro开源项目
  ☆105Updated 4 years ago
• hanun2999 / cadence-skill
  ☆14Updated 2 years ago
• unnir / CadenceSKILL-Python
  Inter Process Communication (IPC) between Python and Cadence Virtuoso
  ☆76Updated 7 years ago
• Werni2A / OpenOrCadParser
  OpenOrCadParser - FOSS Parser for Cadence OrCAD designs.
  ☆56Updated 4 months ago
• freecores / turbo8051
  turbo 8051
  ☆28Updated 7 years ago
• Werni2A / OpenAllegroParser
  OpenAllegroParser - FOSS Parser for Cadence Allegro designs.
  ☆48Updated 2 years ago
• tomzbj / fpm_skills
  Allegro footprints, written in fpm skill.
  ☆12Updated 7 years ago
• suisuisi / FPGAandPeripheralInterface
  Peripheral Interface of FPGA
  ☆32Updated 3 years ago
• suisuisi / jtag
  fpga jtag hardware
  ☆21Updated last year
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆29Updated 5 years ago
• ultraembedded / core_usb_uart
  USB serial device (CDC-ACM)
  ☆36Updated 4 years ago
• cdsdm / cdsdm
  Cadence Virtuoso Design Management System
  ☆33Updated 2 years ago
• ultraembedded / core_ftdi_bridge
  FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge
  ☆27Updated 3 years ago
• PulseRain / Reindeer_Step
  Reindeer Soft CPU for Step CYC10 FPGA board
  ☆27Updated 3 years ago
• mvsoliveira / IBERTpy
  A Python package for running IBERT Eye scan in Vivado, ploting eye diagrams with mathplotlib and compiling results with LaTeX
  ☆12Updated 3 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆39Updated 4 years ago
• yedk / arm_cortex_m0_xillinx
  基于arm cortex-m0内核的xillinx fpga sopc工程项目
  ☆11Updated 5 years ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆29Updated 3 years ago
• unihd-cag / skillbridge
  A seamless python to Cadence Virtuoso Skill interface
  ☆183Updated 6 months ago
• ultraembedded / core_usb_cdc
  Basic USB-CDC device core (Verilog)
  ☆73Updated 3 years ago
• magro732 / OpenRIO
  Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.
  ☆34Updated 7 years ago
• mark-marinas / pe_tools-vcdToPattern
  tool for converting vcd(value change dump) to ate pattern.
  ☆11Updated 9 years ago
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆46Updated 8 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆87Updated 4 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆52Updated 7 years ago
• ebecheto / Skill
  my cadence/virtuoso/icfb skill functions develloped over the years
  ☆116Updated last week