sudharsan2000 / analog-NNLinks
Training Neural Networks using Analog circuits
☆22Updated 4 years ago
Alternatives and similar repositories for analog-NN
Users that are interested in analog-NN are comparing it to the libraries listed below
Sorting:
- Curriculum for a university course to teach chip design using open source EDA tools☆95Updated last year
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆186Updated 2 months ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆78Updated last year
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆122Updated this week
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆203Updated 2 weeks ago
- Introductory course into static timing analysis (STA).☆94Updated 2 weeks ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆99Updated last year
- An overview of TL-Verilog resources and projects☆81Updated 3 months ago
- Verilog implementation of multi-stage 32-bit RISC-V processor☆115Updated 4 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆104Updated 2 months ago
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- SystemVerilog Tutorial☆159Updated 2 months ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆257Updated this week
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆65Updated 2 years ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆180Updated 5 years ago
- ☆151Updated 3 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆43Updated 3 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆101Updated 2 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆132Updated last year
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆27Updated 3 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆59Updated 8 months ago
- Home of the open-source EDA course.☆42Updated last month
- This is a verilog implementation of 4x4 systolic array multiplier☆57Updated 4 years ago
- A Python package to use FPGA development tools programmatically.☆138Updated 3 months ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆73Updated 4 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆38Updated 3 years ago
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆72Updated last month
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆70Updated 4 years ago
- Simple cache design implementation in verilog☆49Updated last year
- Physical Design Flow from RTL to GDS using Opensource tools.☆105Updated 4 years ago