Alternatives and similar repositories for freedom-tools:

Users that are interested in freedom-tools are comparing it to the libraries listed below

• sifive / freedom-u-sdk
  Freedom U Software Development Kit (FUSDK)
  ☆282Updated 3 weeks ago
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆469Updated 3 weeks ago
• riscv-collab / riscv-openocd
  Fork of OpenOCD that has RISC-V support
  ☆461Updated this week
• sifive / freedom-metal
  Bare Metal Compatibility Library for the Freedom Platform
  ☆155Updated last year
• XUANTIE-RV / openc906
  OpenXuantie - OpenC906 Core
  ☆333Updated 7 months ago
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆254Updated 3 weeks ago
• riscv-non-isa / riscv-arch-test
  ☆534Updated last week
• riscv-software-src / riscv-pk
  RISC-V Proxy Kernel
  ☆606Updated 3 months ago
• riscv / riscv-plic-spec
  PLIC Specification
  ☆137Updated last year
• riscvarchive / riscv-platform-specs
  RISC-V Profiles and Platform Specification
  ☆113Updated last year
• sifive / freedom-e-sdk
  Open Source Software for Developing on the Freedom E Platform - Deprecated
  ☆583Updated 6 months ago
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆168Updated last month
• riscvarchive / riscv-gcc
  ☆368Updated last year
• riscvarchive / riscv-software-list
  The RISC-V software tools list, as seen on riscv.org
  ☆461Updated 3 years ago
• embench / embench-iot
  The main Embench repository
  ☆263Updated 5 months ago
• sifive / sifive-blocks
  Common RTL blocks used in SiFive's projects
  ☆181Updated 2 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆238Updated 2 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆167Updated last year
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆147Updated last week
• mariusmm / RISC-V-TLM
  RISC-V SystemC-TLM simulator
  ☆293Updated last month
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆271Updated last year
• RoaLogic / RV12
  RISC-V CPU Core
  ☆304Updated 7 months ago
• riscvarchive / educational-materials
  Educational materials for RISC-V
  ☆224Updated 3 years ago
• chipsalliance / Cores-VeeR-EH2
  ☆222Updated 2 years ago
• riscv / meta-riscv
  OpenEmbedded/Yocto layer for RISC-V Architecture
  ☆374Updated 2 weeks ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆220Updated 2 months ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆177Updated 6 months ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆102Updated last month
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆306Updated last month
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆558Updated 5 months ago