kammoh / chisel-arithmetics
Implementation of low-level hardware arithmatic operations in Chisel
☆8Updated 5 years ago
Related projects ⓘ
Alternatives and complementary repositories for chisel-arithmetics
- BFM Tester for Chisel HDL☆14Updated 2 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 2 years ago
- ☆36Updated 2 years ago
- ☆11Updated 3 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 2 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆23Updated 4 years ago
- Chisel Cheatsheet☆31Updated last year
- Fluid Pipelines☆11Updated 6 years ago
- SVA examples and demonstration☆16Updated 4 years ago
- An automatic clock gating utility☆43Updated 4 months ago
- A coverage library for Chisel designs☆11Updated 4 years ago
- ☆9Updated 2 years ago
- Provides dot visualizations of chisel/firrtl circuites☆11Updated 5 years ago
- ☆9Updated 3 years ago
- APB Logic☆12Updated 9 months ago
- Wake build descriptions of hardware generators☆12Updated 3 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆41Updated 8 months ago
- Examples and design pattern for VHDL verification☆15Updated 8 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- SystemVerilog FSM generator☆26Updated 6 months ago
- ☆13Updated 4 years ago
- ☆9Updated last year
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆11Updated 5 years ago
- Extended and external tests for Verilator testing☆15Updated this week
- Common SystemVerilog RTL modules for RgGen☆11Updated this week
- A configurable SRAM generator☆40Updated this week
- ☆18Updated 4 years ago
- ☆17Updated 3 weeks ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆30Updated 3 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆39Updated 4 years ago