Alternatives and similar repositories for sha256

Users that are interested in sha256 are comparing it to the libraries listed below

• secworks / aes
  Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementatio…
  ☆369Updated 2 months ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆269Updated 4 years ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆305Updated last year
• Digilent / vivado-boards
  ☆445Updated 5 months ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆479Updated 3 years ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆813Updated 3 years ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆427Updated last month
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,082Updated last month
• stffrdhrn / sdram-controller
  Verilog SDRAM memory controller
  ☆335Updated 8 years ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆568Updated 2 months ago
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆457Updated last week
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,310Updated this week
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆623Updated 4 months ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆353Updated last year
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆629Updated last week
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆547Updated 2 months ago
• alexforencich / verilog-uart
  Verilog UART
  ☆492Updated 4 months ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆277Updated 10 months ago
• seldridge / verilog
  Repository for basic (and not so basic) Verilog blocks with high re-use potential
  ☆581Updated 7 years ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆667Updated this week
• fabriziotappero / ip-cores
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆499Updated 2 years ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆810Updated 4 months ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆560Updated 3 weeks ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆582Updated 2 weeks ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,300Updated last week
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,570Updated this week
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆884Updated 2 years ago
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆419Updated last month
• jamieiles / uart
  Verilog UART
  ☆172Updated 12 years ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,604Updated 3 weeks ago