Alternatives and similar repositories for sha256

Users that are interested in sha256 are comparing it to the libraries listed below

• secworks / aes
  Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementatio…
  ☆396Updated 7 months ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆277Updated 5 years ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆606Updated 7 months ago
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆563Updated 3 months ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆676Updated 4 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆621Updated this week
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆446Updated 6 months ago
• secworks / sha1
  Verilog implementation of the SHA-1 cryptgraphic hash function
  ☆55Updated 7 months ago
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆344Updated this week
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆316Updated last year
• Digilent / vivado-boards
  ☆473Updated 4 months ago
• westerndigitalcorporation / swerv_eh1
  A directory of Western Digital’s RISC-V SweRV Cores
  ☆873Updated 5 years ago
• stffrdhrn / sdram-controller
  Verilog SDRAM memory controller
  ☆350Updated 8 years ago
• enjoy-digital / litepcie
  Small footprint and configurable PCIe core
  ☆633Updated 2 weeks ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆747Updated 2 weeks ago
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆457Updated last month
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆673Updated 3 weeks ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆528Updated 4 years ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆331Updated 11 months ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆282Updated last year
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆910Updated 2 years ago
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆466Updated last week
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆693Updated 2 years ago
• seldridge / verilog
  Repository for basic (and not so basic) Verilog blocks with high re-use potential
  ☆599Updated 7 years ago
• chipsalliance / Cores-VeeR-EH2
  ☆247Updated 2 years ago
• VLSI-EDA / PoC
  The PoC Library has been forked to github.com/VHDL/PoC. See new address below
  ☆597Updated 3 months ago
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆283Updated 5 years ago
• subbdue / systemverilog.io
  Code used in
  ☆198Updated 8 years ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆742Updated last month
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆542Updated last month