Alternatives and similar repositories for sha256:

Users that are interested in sha256 are comparing it to the libraries listed below

• secworks / aes
  Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementatio…
  ☆354Updated 3 weeks ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆649Updated 5 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆606Updated last week
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆419Updated last month
• RoaLogic / RV12
  RISC-V CPU Core
  ☆321Updated 10 months ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆682Updated last month
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆697Updated last month
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆299Updated last year
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,049Updated 2 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆480Updated 2 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆544Updated last week
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆271Updated 8 months ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆265Updated 4 years ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆568Updated last week
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆407Updated 6 years ago
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆891Updated 3 weeks ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆247Updated 5 months ago
• fabriziotappero / ip-cores
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆459Updated 2 years ago
• chipsalliance / Cores-VeeR-EH2
  ☆232Updated 2 years ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆274Updated last week
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆598Updated 3 years ago
• kramble / FPGA-Litecoin-Miner
  A litecoin scrypt miner implemented with FPGA on-chip memory.
  ☆288Updated 10 years ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆523Updated last week
• ucb-bar / berkeley-hardfloat
  ☆319Updated 7 months ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆251Updated this week
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆406Updated 3 months ago
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆369Updated this week
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆238Updated 3 weeks ago
• Digilent / vivado-boards
  ☆431Updated 3 months ago
• ridecore / ridecore
  RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
  ☆351Updated 7 years ago