secworks / siphashLinks
Hardware implementation of the SipHash short-inout PRF
☆17Updated 4 months ago
Alternatives and similar repositories for siphash
Users that are interested in siphash are comparing it to the libraries listed below
Sorting:
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Mutation Cover with Yosys (MCY)☆86Updated 3 weeks ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆145Updated 2 weeks ago
- Demo SoC for SiliconCompiler.☆60Updated 2 weeks ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆65Updated 2 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆37Updated 4 years ago
- ☆56Updated 3 years ago
- SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research☆38Updated last year
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- FPGA Assembly (FASM) Parser and Generator☆95Updated 3 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- A Vivado HLS Command Line Helper Tool☆36Updated 3 years ago
- Yet Another RISC-V Implementation☆97Updated 11 months ago
- FGPU is a soft GPU architecture general purpose computing☆60Updated 4 years ago
- Xilinx Unisim Library in Verilog☆85Updated 5 years ago
- OmniXtend cache coherence protocol☆82Updated 2 months ago
- A 32-bit RISC-V processor for mriscv project☆58Updated 8 years ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- The Shang high-level synthesis framework☆120Updated 11 years ago
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆19Updated last year
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- A collection of big designs to run post-synthesis simulations with yosys☆50Updated 9 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆140Updated 11 months ago
- An example OpenCAPI 3.0 FPGA reference design for accelerator endpoint development☆14Updated 2 years ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆111Updated 3 months ago
- Main page☆128Updated 5 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 5 years ago
- An open-source custom cache generator.☆34Updated last year