cliffordwolf / xbitmanipLinks
RISC-V XBitmanip Extension
☆25Updated 6 years ago
Alternatives and similar repositories for xbitmanip
Users that are interested in xbitmanip are comparing it to the libraries listed below
Sorting:
- A time-predictable processor for mixed-criticality systems☆60Updated last year
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)☆20Updated 8 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆38Updated 4 years ago
- A 32-bit RISC-V processor for mriscv project☆60Updated 8 years ago
- An executable specification of the RISCV ISA in L3.☆42Updated 6 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- The BERI and CHERI processor and hardware platform☆50Updated 8 years ago
- Locus site for Public Review of Several RISC-V ISA Formal Specs☆75Updated 5 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆152Updated last week
- Open Processor Architecture☆26Updated 9 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆76Updated 6 years ago
- The preliminary 'RISC-V microcontroller profile' specs; for convenience, use markdown.☆28Updated 3 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- Yet Another RISC-V Implementation☆99Updated last year
- Main page☆129Updated 5 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago
- ☆114Updated 4 years ago
- Documentation for the BOOM processor☆47Updated 8 years ago
- OpenFPGA☆34Updated 7 years ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆119Updated 8 months ago
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆27Updated 5 years ago
- ☆63Updated 7 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 6 years ago
- SoftCPU/SoC engine-V☆55Updated 9 months ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆45Updated 3 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆181Updated 8 months ago
- Lipsi: Probably the Smallest Processor in the World☆89Updated last year
- OmniXtend cache coherence protocol☆82Updated 7 months ago
- RISC-V Frontend Server☆64Updated 6 years ago