cliffordwolf / xbitmanipLinks
RISC-V XBitmanip Extension
☆26Updated 6 years ago
Alternatives and similar repositories for xbitmanip
Users that are interested in xbitmanip are comparing it to the libraries listed below
Sorting:
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆37Updated 4 years ago
- A 32-bit RISC-V processor for mriscv project☆59Updated 8 years ago
- Open Processor Architecture☆26Updated 9 years ago
- A time-predictable processor for mixed-criticality systems☆58Updated 10 months ago
- An executable specification of the RISCV ISA in L3.☆42Updated 6 years ago
- The BERI and CHERI processor and hardware platform☆50Updated 8 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆75Updated 6 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)☆20Updated 8 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆147Updated last month
- A Verilog Synthesis Regression Test☆37Updated last year
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- Locus site for Public Review of Several RISC-V ISA Formal Specs☆75Updated 5 years ago
- Mutation Cover with Yosys (MCY)☆87Updated last month
- The preliminary 'RISC-V microcontroller profile' specs; for convenience, use markdown.☆28Updated 3 years ago
- Documentation for the BOOM processor☆47Updated 8 years ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- Yet Another RISC-V Implementation☆97Updated last year
- OpenFPGA☆34Updated 7 years ago
- A tiny POWER Open ISA soft processor written in Chisel☆110Updated 2 years ago
- A utility for Composing FPGA designs from Peripherals☆184Updated 9 months ago
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆27Updated 4 years ago
- A reimplementation of a tiny stack CPU☆85Updated last year
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆115Updated 4 months ago
- ☆64Updated 6 years ago
- OmniXtend cache coherence protocol☆82Updated 3 months ago
- Main page☆128Updated 5 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆123Updated 9 years ago