sarlinpe / Hardware-Neural-Network
Embedded hardware accelerator of multilayer perceptrons for lightweight machine learning
☆16Updated 8 years ago
Alternatives and similar repositories for Hardware-Neural-Network:
Users that are interested in Hardware-Neural-Network are comparing it to the libraries listed below
- Caffe to VHDL☆67Updated 4 years ago
- ☆83Updated 4 years ago
- verilog CNN generator for FPGA☆34Updated 4 years ago
- ☆45Updated 5 years ago
- This repo is for ECE44x (Fall2015-Spring2016)☆20Updated 7 years ago
- ☆105Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- Verilog Convolutional Neural Network on PYNQ☆28Updated 7 years ago
- RTL implementation of TFlite FPGA accelerator and RISC-V controller. 3D Object Detection based on LiDAR Point Clouds.☆12Updated 2 years ago
- ☆65Updated 2 years ago
- ☆87Updated 5 years ago
- Systolic-array based Deep Learning Accelerator generator☆24Updated 4 years ago
- SDSoC™ (Software-Defined System-On-Chip) Environment Tutorials☆151Updated 5 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆104Updated 6 years ago
- This project is trying to create a base vitis platform to run with DPU☆46Updated 4 years ago
- Demonstration of the AXI DMA engine on the ZedBoard☆53Updated 4 years ago
- Xilinx Deep Learning IP☆91Updated 3 years ago
- Huffman encoding core (Vivado HLS Project)☆12Updated 5 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆25Updated 4 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆91Updated 5 years ago
- Adding PR to the PYNQ Overlay☆17Updated 8 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆30Updated 4 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆21Updated 5 years ago
- RTL Verilog library for various DSP modules☆86Updated 3 years ago
- A multi-board Extended Kalman Filter (EKF)☆31Updated 6 years ago
- ☆16Updated 4 years ago
- Residual Binarized Neural Network☆43Updated 7 years ago
- ☆63Updated 6 years ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆107Updated 5 years ago
- DMA enabled Zynq PS-PL communication to implement high throughput data transfer between Linux applications and user IP core.☆39Updated 8 years ago