kmursi / ML_Attack_XOR_PUF

Related projects ⓘ

Alternatives and complementary repositories for ML_Attack_XOR_PUF

• IFM-Ulm / ro-pr-fw
  Framework based on Partial Reconfiguration for chip characterization utilizing ring-oscillator PUFs
  ☆10Updated 4 years ago
• scluconn / LPN-based_PUF
  FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.
  ☆15Updated 7 years ago
• eriksargent / PUF-lab
  FPGA implementation of a physical unclonable function for authentication
  ☆32Updated 7 years ago
• scluconn / DA_PUF_Library
  Defense/Attack PUF Library (DA PUF Library)
  ☆46Updated 4 years ago
• Praneshss / Modeling_of_APUF_Compositions
  Python Code and Dataset for different PUFs
  ☆16Updated 3 years ago
• KULeuven-COSIC / COSO-TRNG
  Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.
  ☆12Updated this week
• siamumar / BIST_PUF_TRNG
  A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators
  ☆21Updated 6 years ago
• p4r4xor / Montgomery1024
  Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation
  ☆10Updated 4 years ago
• crypt-xie / XCryptCore
  Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)
  ☆35Updated 4 years ago
• ANSSI-FR / IPECC
  A VHDL IP for ECC (Elliptic Curve Cryptography) hardware acceleration
  ☆29Updated 4 months ago
• ovpanait / zynq-aes
  AES hardware engine for Xilinx Zynq platform
  ☆28Updated 3 years ago
• nolancon / AES128
  C++ and Verilog to implement AES128
  ☆16Updated 6 years ago
• zdszx / Modexpowering3
  a 2048 bit RSA verilog project basing on Montgomery , Karatsuba multiplier
  ☆16Updated 2 years ago
• shiva-t / Elliptical-Curve-Cryptography-FPGA
  Implementation of ECC on FPGA-Zynq7000 SoC
  ☆17Updated 5 years ago
• Crimsonninja / senior_design_puf
  Repository to store all design and testbench files for Senior Design
  ☆17Updated 4 years ago
• pnvamshi / Hardware-Implementation-of-AES-Verilog
  Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog
  ☆37Updated 7 years ago
• ljgibbslf / SM2_core
  opensource crypto IP core
  ☆26Updated 4 years ago
• ahegazy / aes
  Advanced encryption standard implementation in verilog.
  ☆27Updated 2 years ago
• kemalderya / pqc-param-ntt
  ☆18Updated 2 years ago
• hadipourh / AES-VHDL
  VHDL Implementation of AES Algorithm
  ☆72Updated 3 years ago
• raymondrc / FPGA_SM4
  FPGA implementation of Chinese SM4 encryption algorithm.
  ☆46Updated 6 years ago
• ecelab-org / Split-Chip_authentication
  An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.
  ☆15Updated 5 years ago
• adnanbaysal / TRNG-with-Ring-Oscillators-in-Verilog
  A true random number generator with ring oscillators structure written in VHDL targeting FPGA's.
  ☆9Updated 4 years ago
• Gabalo / RO_PUF
  Ring Oscillator Physically Unclonable Funtion
  ☆18Updated 3 years ago
• XBQ314 / A-Number-Theoretic-Transform-Accelerator-with-Two-Parallel-Simplified-Butterfly-Units
  Implementation of Number-theoretic transform(NTT) algorithm on FPGA; 快速数论变换(NTT)的FPGA实现，基为2，有两个并行的蝶形单元
  ☆14Updated 2 years ago
• raymondrc / FPGA-SM3-HASH
  Description of Chinese SM3 Hash algorithm with Verilog HDL
  ☆45Updated 6 years ago
• fatestudio / RSA4096_NEW
  ☆12Updated 9 years ago
• gongxunwu / sm4-verilog
  ☆20Updated 5 years ago
• raymondrc / riscv-isa-extension-for-SM4
  RISC-V instruction set extensions for SM4 block cipher
  ☆18Updated 4 years ago
• mematrix / AES-FPGA
  AES加密解密算法的Verilog实现
  ☆60Updated 8 years ago