kmursi / ML_Attack_XOR_PUF
The ML_Attack_XOR_PUF is a Machine Learning-based model for attacking the XOR Physical Unclonable Functions using a small number of challenge-response-pair and short computation time.
☆15Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for ML_Attack_XOR_PUF
- FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.☆15Updated 7 years ago
- Python Code and Dataset for different PUFs☆16Updated 3 years ago
- A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators☆21Updated 6 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆10Updated 4 years ago
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆36Updated 7 years ago
- FPGA implementation of a physical unclonable function for authentication☆31Updated 7 years ago
- Defense/Attack PUF Library (DA PUF Library)☆45Updated 4 years ago
- Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.☆12Updated 5 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆35Updated 4 years ago
- Implementation of Number-theoretic transform(NTT) algorithm on FPGA; 快速数论变换(NTT)的FPGA实现,基为2,有两个并行的蝶形单元☆14Updated 2 years ago
- An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.☆15Updated 4 years ago
- ☆12Updated 9 years ago
- High-speed full CRYSTALS-DILITHIUM implementation on FPGA: Keygen, Sign, Verify.☆41Updated last year
- Implementation of ECC on FPGA-Zynq7000 SoC☆17Updated 5 years ago
- Repository to store all design and testbench files for Senior Design☆17Updated 4 years ago
- True Random Number Generator core implemented in Verilog.☆72Updated 4 years ago
- This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…☆29Updated 6 years ago
- AES hardware engine for Xilinx Zynq platform☆28Updated 3 years ago
- A true random number generator with ring oscillators structure written in VHDL targeting FPGA's.☆9Updated 4 years ago
- VexRiscv reference platforms for the pqriscv project☆15Updated 8 months ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆27Updated 8 months ago
- AES加密解密算法的Verilog实现☆58Updated 8 years ago
- a 2048 bit RSA verilog project basing on Montgomery , Karatsuba multiplier☆16Updated 2 years ago
- Implementation of RSA algorithm on FPGA using Verilog☆26Updated 6 years ago
- Verilog Implementation of modular exponentiation using Montgomery multiplication☆32Updated 10 years ago
- ☆20Updated 5 years ago
- RISC-V instruction set extensions for SM4 block cipher☆18Updated 4 years ago
- An FPGA Implementation of Arbiter PUF with 4x4 Switch Blocks☆14Updated 4 years ago
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆21Updated last month
- NIST LWC Hardware Design of Ascon with Protection against Power Side-Channel Attacks☆14Updated last year