Alternatives and similar repositories for ML_Attack_XOR_PUF:

Users that are interested in ML_Attack_XOR_PUF are comparing it to the libraries listed below

• Praneshss / Modeling_of_APUF_Compositions
  Python Code and Dataset for different PUFs
  ☆17Updated 3 years ago
• scluconn / LPN-based_PUF
  FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.
  ☆15Updated 7 years ago
• scluconn / DA_PUF_Library
  Defense/Attack PUF Library (DA PUF Library)
  ☆49Updated 4 years ago
• siamumar / BIST_PUF_TRNG
  A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators
  ☆22Updated 7 years ago
• IFM-Ulm / ro-pr-fw
  Framework based on Partial Reconfiguration for chip characterization utilizing ring-oscillator PUFs
  ☆10Updated 5 years ago
• Gabalo / RO_PUF
  Ring Oscillator Physically Unclonable Funtion
  ☆23Updated 3 years ago
• eriksargent / PUF-lab
  FPGA implementation of a physical unclonable function for authentication
  ☆32Updated 8 years ago
• XBQ314 / A-Number-Theoretic-Transform-Accelerator-with-Two-Parallel-Simplified-Butterfly-Units
  Implementation of Number-theoretic transform(NTT) algorithm on FPGA; 快速数论变换(NTT)的FPGA实现，基为2，有两个并行的蝶形单元
  ☆19Updated 2 years ago
• p4r4xor / Montgomery1024
  Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation
  ☆10Updated 5 years ago
• shiva-t / Elliptical-Curve-Cryptography-FPGA
  Implementation of ECC on FPGA-Zynq7000 SoC
  ☆17Updated 5 years ago
• AnuragSChatterjee / Multilayer-Perception-MLP-Neural-Network-Implementation-In-FPGA
  A final semester based group project for EE4218: Embedded Hardware System Design module in NUS where I worked with my teammate to perform…
  ☆14Updated last year
• Crimsonninja / senior_design_puf
  Repository to store all design and testbench files for Senior Design
  ☆18Updated 5 years ago
• kgpai94 / ECC-Encryption-System
  This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…
  ☆31Updated 6 years ago
• adnanbaysal / TRNG-with-Ring-Oscillators-in-Verilog
  A true random number generator with ring oscillators structure written in VHDL targeting FPGA's.
  ☆10Updated 4 years ago
• fatestudio / RSA4096_NEW
  ☆13Updated 10 years ago
• ecelab-org / Split-Chip_authentication
  An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.
  ☆16Updated 5 years ago
• crypt-xie / XCryptCore
  Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)
  ☆38Updated 5 years ago
• VLSIDA / puffery
  Tools for PUF analysis
  ☆11Updated 3 years ago
• aneeshkandi14 / ascon-hw-public
  ☆21Updated 9 months ago
• GMUCERG / Dilithium
  High-speed full CRYSTALS-DILITHIUM implementation on FPGA: Keygen, Sign, Verify.
  ☆52Updated 2 years ago
• KULeuven-COSIC / COSO-TRNG
  Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.
  ☆13Updated 5 months ago
• ovpanait / zynq-aes
  AES hardware engine for Xilinx Zynq platform
  ☆30Updated 3 years ago
• nolancon / AES128
  C++ and Verilog to implement AES128
  ☆22Updated 6 years ago
• kemalderya / pqc-param-ntt
  ☆21Updated 3 years ago
• karanahujax / PUF
  Cryptographic Key Generation from PUF Data
  ☆21Updated 5 years ago
• zdszx / Modexpowering3
  a 2048 bit RSA verilog project basing on Montgomery , Karatsuba multiplier
  ☆22Updated 3 years ago
• momalab / CoPHEE
  CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.
  ☆31Updated last year
• secworks / ascon
  Verilog implementation of the ASCON lightweight authenticated encryption and hashing algorithm
  ☆10Updated 5 months ago
• pnvamshi / Hardware-Implementation-of-AES-Verilog
  Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog
  ☆39Updated 7 years ago
• hyperpicc / ecc
  Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)
  ☆19Updated 7 years ago