Alternatives and similar repositories for ML_Attack_XOR_PUF:

Users that are interested in ML_Attack_XOR_PUF are comparing it to the libraries listed below

• IFM-Ulm / ro-pr-fw
  Framework based on Partial Reconfiguration for chip characterization utilizing ring-oscillator PUFs
  ☆10Updated 4 years ago
• Praneshss / Modeling_of_APUF_Compositions
  Python Code and Dataset for different PUFs
  ☆16Updated 3 years ago
• eriksargent / PUF-lab
  FPGA implementation of a physical unclonable function for authentication
  ☆33Updated 7 years ago
• siamumar / BIST_PUF_TRNG
  A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators
  ☆21Updated 7 years ago
• scluconn / LPN-based_PUF
  FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.
  ☆15Updated 7 years ago
• karanahujax / PUF
  Cryptographic Key Generation from PUF Data
  ☆20Updated 5 years ago
• scluconn / DA_PUF_Library
  Defense/Attack PUF Library (DA PUF Library)
  ☆47Updated 4 years ago
• Gabalo / RO_PUF
  Ring Oscillator Physically Unclonable Funtion
  ☆18Updated 3 years ago
• ecelab-org / Split-Chip_authentication
  An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.
  ☆15Updated 5 years ago
• KULeuven-COSIC / COSO-TRNG
  Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.
  ☆12Updated 2 months ago
• adnanbaysal / TRNG-with-Ring-Oscillators-in-Verilog
  A true random number generator with ring oscillators structure written in VHDL targeting FPGA's.
  ☆10Updated 4 years ago
• AnuragSChatterjee / Multilayer-Perception-MLP-Neural-Network-Implementation-In-FPGA
  A final semester based group project for EE4218: Embedded Hardware System Design module in NUS where I worked with my teammate to perform…
  ☆13Updated last year
• p4r4xor / Montgomery1024
  Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation
  ☆10Updated 5 years ago
• A-suozhang / Verilog_Uart_With_Fifo
  Implemented The UART with FIFO
  ☆12Updated 5 years ago
• ovpanait / zynq-aes
  AES hardware engine for Xilinx Zynq platform
  ☆29Updated 3 years ago
• Crimsonninja / senior_design_puf
  Repository to store all design and testbench files for Senior Design
  ☆18Updated 4 years ago
• nolancon / AES128
  C++ and Verilog to implement AES128
  ☆19Updated 6 years ago
• shiva-t / Elliptical-Curve-Cryptography-FPGA
  Implementation of ECC on FPGA-Zynq7000 SoC
  ☆17Updated 5 years ago
• kgpai94 / ECC-Encryption-System
  This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…
  ☆31Updated 6 years ago
• zdszx / Modexpowering3
  a 2048 bit RSA verilog project basing on Montgomery , Karatsuba multiplier
  ☆20Updated 2 years ago
• crypt-xie / XCryptCore
  Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)
  ☆38Updated 5 years ago
• canaknesil / 4x4-apuf
  An FPGA Implementation of Arbiter PUF with 4x4 Switch Blocks
  ☆15Updated 4 years ago
• fatestudio / RSA4096_NEW
  ☆12Updated 9 years ago
• freecores / sha3
  SHA3 (KECCAK)
  ☆16Updated 10 years ago
• mashahedurrahman / Security-Engine
  ☆11Updated 9 months ago
• pnvamshi / Hardware-Implementation-of-AES-Verilog
  Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog
  ☆38Updated 7 years ago
• aneeshkandi14 / ascon-hw-public
  ☆20Updated 7 months ago
• lajanugen / Modular-Exponentiation
  Verilog Implementation of modular exponentiation using Montgomery multiplication
  ☆32Updated 10 years ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆44Updated 3 years ago
• avashist003 / SystemVerilog_Design_Verification
  Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog
  ☆24Updated 2 years ago