robertdunne / FPGA-ARM
Verilog source code for book: Computer Architecture Tutorial
☆25Updated 3 years ago
Alternatives and similar repositories for FPGA-ARM:
Users that are interested in FPGA-ARM are comparing it to the libraries listed below
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Updated last year
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆43Updated last year
- Exercises of the FPGA Prototyping By Verilog Examples book by Pong P. Chu☆20Updated 6 years ago
- Wishbone interconnect utilities☆38Updated 7 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆76Updated last year
- RISC V core implementation using Verilog.☆26Updated 3 years ago
- This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop☆34Updated 3 years ago
- Verilog Modules and Python Scripts for Creating IP Core Build Directories☆29Updated last year
- Cache Controller for a multi-level Cache memory using four-way set-associative mapping with write-back, no-write allocate and LRU policy.…☆8Updated 4 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆21Updated 3 months ago
- IP operations in verilog (simulation and implementation on ice40)☆54Updated 5 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆76Updated 2 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆44Updated 2 months ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆61Updated 4 years ago
- SoftCPU/SoC engine-V☆54Updated last year
- 3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.☆72Updated 4 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆57Updated last month
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆62Updated 4 years ago
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆34Updated 4 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆50Updated last year
- I2C controller core☆36Updated 2 years ago
- ☆58Updated 3 years ago
- Simple 8-bit UART realization on Verilog HDL.☆93Updated 8 months ago
- M-extension for RISC-V cores.☆23Updated last month
- Basic USB 1.1 Host Controller for small FPGAs☆86Updated 4 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆72Updated 9 months ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆79Updated 4 years ago
- Hamming ECC Encoder and Decoder to protect memories☆29Updated 3 months ago
- Engineering Program on RTL Design for FPGA Accelerator☆26Updated 4 years ago
- SDRAM controller optimized to a memory bandwidth of 316MB/s☆25Updated 3 years ago