robertdunne / FPGA-ARM
Verilog source code for book: Computer Architecture Tutorial
☆25Updated 3 years ago
Alternatives and similar repositories for FPGA-ARM
Users that are interested in FPGA-ARM are comparing it to the libraries listed below
Sorting:
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Updated 2 years ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆46Updated last year
- This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop☆36Updated 3 years ago
- Another tiny RISC-V implementation☆55Updated 3 years ago
- Exercises of the FPGA Prototyping By Verilog Examples book by Pong P. Chu☆21Updated 6 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆84Updated last week
- Basic RISC-V Test SoC☆122Updated 6 years ago
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆74Updated 2 years ago
- Wishbone interconnect utilities☆41Updated 3 months ago
- USB -> AXI Debug Bridge☆38Updated 3 years ago
- Basic Verilog Ethernet core and C driver functions☆11Updated 2 months ago
- Minimal DVI / HDMI Framebuffer☆81Updated 4 years ago
- Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application☆48Updated 11 months ago
- 3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.☆79Updated 4 years ago
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆37Updated 4 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆88Updated last year
- Cache Controller for a multi-level Cache memory using four-way set-associative mapping with write-back, no-write allocate and LRU policy.…☆9Updated 4 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆78Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 3 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆90Updated this week
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆55Updated last year
- Simple RiscV core for academic purpose.☆22Updated 5 years ago
- I2C controller core☆39Updated 2 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 5 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆80Updated 4 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆91Updated 3 weeks ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆29Updated 4 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 4 months ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 5 years ago