arm-university / Modern-System-on-Chip-Design-on-Arm
A textbook on system on chip design using Arm Cortex-A
☆26Updated 10 months ago
Alternatives and similar repositories for Modern-System-on-Chip-Design-on-Arm:
Users that are interested in Modern-System-on-Chip-Design-on-Arm are comparing it to the libraries listed below
- A reference book on System-on-Chip Design☆25Updated 11 months ago
- SystemC training aimed at TLM.☆27Updated 4 years ago
- HLS for Networks-on-Chip☆33Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆53Updated 2 weeks ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆33Updated last year
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆31Updated last month
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- Ratatoskr NoC Simulator☆24Updated 3 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆64Updated last month
- DUTH RISC-V Superscalar Microprocessor☆30Updated 5 months ago
- cycle accurate Network-on-Chip Simulator☆27Updated last year
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆36Updated 5 months ago
- ☆26Updated 5 years ago
- SoC design & prototyping☆12Updated 3 years ago
- Development of a Network on Chip Simulation using SystemC.☆31Updated 7 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆31Updated 2 months ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆49Updated 7 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆26Updated 6 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- BlackParrot on Zynq☆35Updated 3 weeks ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆22Updated 6 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆25Updated 5 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆51Updated 3 years ago
- ☆3Updated 3 years ago
- Xilinx AXI VIP example of use☆34Updated 3 years ago
- Archives of SystemC from The Ground Up Book Exercises☆30Updated 2 years ago
- ☆11Updated 4 months ago
- ☆24Updated last month
- Chisel implementation of Neural Processing Unit for System on the Chip☆21Updated this week