arm-university / Modern-System-on-Chip-Design-on-ArmLinks
A textbook on system on chip design using Arm Cortex-A
☆40Updated 5 months ago
Alternatives and similar repositories for Modern-System-on-Chip-Design-on-Arm
Users that are interested in Modern-System-on-Chip-Design-on-Arm are comparing it to the libraries listed below
Sorting:
- SoC design & prototyping☆16Updated 5 months ago
- Learn systemC with examples☆124Updated 2 years ago
- A reference book on System-on-Chip Design☆36Updated 5 months ago
- A repository for SystemC Learning examples☆72Updated 3 years ago
- Advanced Architecture Labs with CVA6☆71Updated last year
- BlackParrot on Zynq☆47Updated last week
- Verilog/SystemVerilog Guide☆75Updated last year
- SystemC training aimed at TLM.☆34Updated 5 years ago
- PCI Express controller model☆69Updated 3 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆75Updated last month
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆113Updated 2 years ago
- Brief SystemC getting started tutorial☆95Updated 6 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆20Updated 2 weeks ago
- QEMU libsystemctlm-soc co-simulation demos.☆156Updated 6 months ago
- Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…☆115Updated last month
- matrix-coprocessor for RISC-V☆25Updated 7 months ago
- ☆31Updated 5 years ago
- ☆69Updated 4 years ago
- ☆57Updated 6 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- An open-source UCIe controller implementation☆76Updated last week
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆124Updated this week
- HLS for Networks-on-Chip☆37Updated 4 years ago
- ☆78Updated 11 years ago
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆191Updated last week
- Two Level Cache Controller implementation in Verilog HDL☆53Updated 5 years ago
- A modeling library with virtual components for SystemC and TLM simulators☆174Updated this week
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆47Updated 3 weeks ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆93Updated 3 weeks ago