shioyadan / menoLinks
Meno is a tool for visualizing hierarchical data, such as synthesized circuit sizes. It can be built into a single, standalone HTML file. Currently, Meno supports hierarchical area reports from Vivado, Genus, and DC, and hierarchical power reports from PrimeTime.
☆16Updated last month
Alternatives and similar repositories for meno
Users that are interested in meno are comparing it to the libraries listed below
Sorting:
- Basic Common Modules☆45Updated this week
- This is my first trial project for designing RISC-V in Chisel☆17Updated last year
- Original FPGA platform☆70Updated last week
- RISC-V RV32IMAFC Core for MCU☆40Updated 10 months ago
- 10G Ethernet MAC implementation☆22Updated 5 years ago
- The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.☆45Updated 4 years ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- Polyphony is Python based High-Level Synthesis compiler.☆108Updated 10 months ago
- Binary Neural Network Framework for FPGA(Differentiable LUT)☆165Updated 4 months ago
- SystemVerilog synthesis tool☆220Updated 9 months ago
- Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for F…☆108Updated 3 years ago
- みんなのSystemVerilog☆19Updated 3 years ago
- Source Codes for a lecture entitled "Parallel and Reconfigurable VLSI Computing" in Tokyo Tech.☆28Updated 4 years ago
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆141Updated last week
- SystemVerilog language server client for Visual Studio Code☆23Updated 2 years ago
- An automatic clock gating utility☆51Updated 7 months ago
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 10 years ago
- SystemVerilog frontend for Yosys☆178Updated this week
- Network on Chip Implementation written in SytemVerilog☆195Updated 3 years ago
- Framework to perform DUT vs ISS (Whisper) lockstep architectural checks☆21Updated last month
- RISC-V Directed Test Framework and Compliance Suite, RiESCUE☆39Updated last week
- A SystemVerilog source file pickler.☆60Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated last week
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆95Updated last year
- RISC-V Verification Interface☆126Updated 3 weeks ago
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- Code generation tool for control and status registers☆435Updated last week
- RISC-V Nox core☆69Updated 4 months ago
- ☆110Updated last month
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago