Alternatives and similar repositories for meno:

Users that are interested in meno are comparing it to the libraries listed below

• pezy-computing / pzbcm
  Basic Common Modules
  ☆37Updated 5 months ago
• diningyo / dirv
  This is my first trial project for designing RISC-V in Chisel
  ☆17Updated last year
• vengineer-systemverilog / All-of-SystemVerilog
  みんなのSystemVerilog
  ☆19Updated 2 years ago
• panda5mt / KyogenRV
  The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
  ☆45Updated 4 years ago
• ryuz / jelly
  Original FPGA platform
  ☆62Updated this week
• nlsynth / karuta
  Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for F…
  ☆105Updated 3 years ago
• dalance / svls-vscode
  SystemVerilog language server client for Visual Studio Code
  ☆20Updated 2 years ago
• polyphony-dev / polyphony
  Polyphony is Python based High-Level Synthesis compiler.
  ☆104Updated 3 months ago
• munetomo-maruyama / mmRISC-1
  RISC-V RV32IMAFC Core for MCU
  ☆36Updated 3 months ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆40Updated last year
• snishizawa / libretto
  Characterizer
  ☆22Updated 8 months ago
• Nic30 / hwtHls
  LLVM based HLS library for HWToolkit (hardware devel. toolkit)
  ☆25Updated 5 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆41Updated 2 years ago
• tenstorrent / cosim-arch-checker
  Framework to perform DUT vs ISS (Whisper) lockstep architectural checks
  ☆17Updated 2 months ago
• fixstars / xg_mac
  10G Ethernet MAC implementation
  ☆21Updated 4 years ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• kadomoto / poyo-v
  Open source RISC-V IP core for FPGA/ASIC design
  ☆30Updated 9 months ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 4 years ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆55Updated last year
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆47Updated 3 weeks ago
• pezy-computing / flgen
  Filelist generator
  ☆16Updated last month
• nlsynth / iroha
  Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)
  ☆35Updated 3 years ago
• onikiri / onikiri2
  ☆39Updated 8 months ago
• uenoku / firtool-standalone-plugin
  an experiment to run plugin in firtool pipeline
  ☆9Updated last year
• Kuree / kratos
  Debuggable hardware generator
  ☆69Updated 2 years ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated 2 months ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• openrisc / or1k_marocchino
  OpenRISC processor IP core based on Tomasulo algorithm
  ☆32Updated 3 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆56Updated 6 months ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated this week