Meno is a tool for visualizing hierarchical data, such as synthesized circuit sizes. It can be built into a single, standalone HTML file. Currently, Meno supports hierarchical area reports from Vivado, Genus, and DC, and hierarchical power reports from PrimeTime.
☆21Sep 28, 2026Updated 2 weeks ago
Alternatives and similar repositories for meno
Users that are interested in meno are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Basic Common Modules☆48Oct 5, 2026Updated last week
- Verilua: An Open Source Versatile Framework for Efficient Hardware Verification and Analysis Using LuaJIT☆22Oct 8, 2026Updated last week
- ☆20Nov 27, 2023Updated 2 years ago
- ☆22Sep 26, 2025Updated last year
- AMD Generic Encapsulated Software Architecture Platform Security Processor Configuration Block manipulation library☆20Dec 18, 2025Updated 9 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Filelist generator☆21Updated this week
- Useful UVM extensions☆28Jul 10, 2024Updated 2 years ago
- Rust library for parsing a number of firmware images☆16Feb 22, 2023Updated 3 years ago
- This is my first trial project for designing RISC-V in Chisel☆17Apr 29, 2024Updated 2 years ago
- A Verilog Filelist parser in Rust☆11Mar 25, 2022Updated 4 years ago
- Let's write RISC-V CPU in Veryl!☆75Jul 24, 2026Updated 2 months ago
- [MIGRATED to https://codeberg.org/prjunnamed/prjunnamed] End-to-end synthesis and P&R toolchain☆95Mar 12, 2026Updated 7 months ago
- SurgeFuzz: Surge-Aware Directed Fuzzing for CPU Designs (ICCAD 2023)☆23Dec 5, 2024Updated last year
- 🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl☆126Oct 3, 2026Updated 2 weeks ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- This is the Verilog 2005 parser used by VerilogCreator☆15May 19, 2019Updated 7 years ago
- Translation of http://chip-architect.com/news/2003_09_21_Detailed_Architecture_of_AMDs_64bit_Core.html☆11Feb 5, 2019Updated 7 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- Porting FreeRTOS to a RISC-V based system on PYNQ-Z2☆13Dec 26, 2024Updated last year
- Microprobe: Microbenchmark generation framework☆28Feb 5, 2026Updated 8 months ago
- Library of High Precision Sparse Matrix Operations Accelerated by SIMD☆44Jun 18, 2021Updated 5 years ago
- This upload contains the artifacts for the paper "SLAP: Data Speculation Attacks via Load Address Prediction on Apple Silicon", to appear…☆27Jan 26, 2025Updated last year
- Framework to perform DUT vs ISS (Whisper) lockstep architectural checks☆26Oct 15, 2025Updated last year
- ☆15Jan 11, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- a multiplier÷r verilog RTL file for RV32M instructions☆14Mar 17, 2020Updated 6 years ago
- Proof-of-concept implementation for the paper "Efficient and Generic Microarchitectural Hash-Function Recovery" (IEEE S&P 2024)☆33Aug 30, 2023Updated 3 years ago
- Text describing xv6 on RISC-V☆16Jul 23, 2020Updated 6 years ago
- An example of on-boarding a PIO block in with duh and wake☆12Nov 18, 2020Updated 5 years ago
- The code in this project demonstrates 2 novel Spectre-V4 attacks, named as out-of-place Spectre-STL and Spectre-CTL, based on the Specula…☆23Nov 23, 2023Updated 2 years ago
- Determines the modules declared and instantiated in a SystemVerilog file☆51Sep 23, 2024Updated 2 years ago
- Helper of yaml file generation from single master yaml file.☆10Mar 17, 2020Updated 6 years ago
- Inference code for DeepCoro☆20Jul 6, 2024Updated 2 years ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆40Oct 8, 2026Updated last week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Source codes for "Bouquet of Instruction Pointers"☆17Nov 4, 2020Updated 5 years ago
- Logic circuit analysis and optimization☆53Feb 2, 2026Updated 8 months ago
- GPU移植のための実装例（直接法に基づくN体計算）☆17Aug 17, 2026Updated 2 months ago
- A git subcommand to apply skeleton repository continuously☆15Sep 14, 2026Updated last month
- JSON5 parser for Ruby☆18Sep 14, 2026Updated last month
- PipeProof☆11Dec 18, 2019Updated 6 years ago
- LL(k) and LALR(1) parser generator for Rust and C#☆236Updated this week