Alternatives and similar repositories for thead-extension-spec

Users that are interested in thead-extension-spec are comparing it to the libraries listed below

• XUANTIE-RV / xuantie-gnu-toolchain
  GNU toolchain for Xuantie RISC-V CPU, including GCC and Binutils ……
  ☆104Updated 8 months ago
• riscv-non-isa / riscv-c-api-doc
  Documentation of the RISC-V C API
  ☆78Updated this week
• riscvarchive / riscv-CMOs
  ☆89Updated 3 months ago
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆39Updated last year
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆152Updated last month
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆61Updated 3 years ago
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆42Updated 2 weeks ago
• XUANTIE-RV / tvm
  TVM for chips base on Xuantie CPU, an open deep learning compiler stack.
  ☆30Updated last year
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆93Updated 6 months ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated last month
• cnrv / RVSC2023
  RISC-V Summit China 2023
  ☆40Updated 2 years ago
• riscv / riscv-test-env
  ☆51Updated 2 months ago
• riscv / riscv-aia
  ☆98Updated 3 months ago
• cnrv / RISCV-East-Asia-Biweekly-Sync
  Biweekly Sync Meeting for RISC-V Software Ecosystem. Meeting time is more friendly for people living in East Asia.
  ☆23Updated 2 weeks ago
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆107Updated 2 months ago
• anishathalye / bin2coe
  A tool to convert binary files to COE files 💫
  ☆17Updated 2 weeks ago
• XUANTIE-RV / qemu
  Qemu for Xuantie RISC-V CPU, a generic machine emulator and virtualizer.
  ☆49Updated 4 months ago
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆55Updated 11 months ago
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆22Updated 8 months ago
• riscvarchive / riscv-edk2-platforms
  Port of EDK2 implementation of UEFI to RISC-V. See documentation at:
  ☆18Updated 4 years ago
• CTSRD-CHERI / SIMTight
  Synthesisable SIMT-style RISC-V GPGPU
  ☆44Updated 5 months ago
• XUANTIE-RV / zero_stage_boot
  ☆15Updated last week
• openhwgroup / cv32e40x-dv
  CV32E40X Design-Verification environment
  ☆16Updated last year
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆71Updated last year
• riscv-non-isa / riscv-uefi
  ☆34Updated 3 years ago
• riscv-non-isa / riscv-semihosting
  ☆32Updated this week
• XUANTIE-RV / csi-nn2
  An optimized neural network operator library for chips base on Xuantie CPU.
  ☆96Updated last year
• c-sky / xuantie-vector-demos
  ☆10Updated 5 years ago
• riscv-admin / riscv-ovpsim
  ☆61Updated 4 years ago