Alternatives and similar repositories for thead-extension-spec:

Users that are interested in thead-extension-spec are comparing it to the libraries listed below

• riscv-non-isa / riscv-uefi
  ☆28Updated 2 years ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆64Updated this week
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆52Updated 4 years ago
• embecosm / riscv-gdbserver
  GDB Server for interacting with RISC-V models, boards and FPGAs
  ☆21Updated 5 years ago
• riscv-non-isa / riscv-semihosting
  ☆28Updated 2 months ago
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆36Updated last year
• riscvarchive / riscv-edk2-platforms
  Port of EDK2 implementation of UEFI to RISC-V. See documentation at:
  ☆18Updated 3 years ago
• riscv / riscv-CMOs
  ☆82Updated 2 years ago
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆47Updated 2 weeks ago
• bluespec / RISCV_gdbstub
  A gdbstub for connecting GDB to a RISC-V Debug Module
  ☆25Updated 3 months ago
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆34Updated 11 months ago
• XUANTIE-RV / xuantie-yocto
  Yocto project for Xuantie RISC-V CPU
  ☆38Updated 2 weeks ago
• riscvarchive / riscv-zicond
  The ISA specification for the ZiCondOps extension.
  ☆19Updated 9 months ago
• pulp-platform / trace_debugger
  Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
  ☆18Updated 10 months ago
• chipsalliance / rocket-chip-blocks
  RTL blocks compatible with the Rocket Chip Generator
  ☆14Updated 6 months ago
• riscv / riscv-aclint
  ☆42Updated 3 years ago
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆34Updated 4 months ago
• riscv / riscv-test-env
  ☆43Updated 3 weeks ago
• pulp-platform / trdb
  RISC-V processor tracing tools and library
  ☆16Updated 10 months ago
• riscv / riscv-smmtt
  This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…
  ☆42Updated last month
• jiegec / jtag-remote-server
  Remote JTAG server for remote debugging
  ☆35Updated 8 months ago
• riscv / riscv-aia
  ☆85Updated 2 months ago
• XUANTIE-RV / xuantie-gnu-toolchain
  GNU toolchain for Xuantie RISC-V CPU, including GCC and Binutils ……
  ☆93Updated last month
• sophgocommunity / SG2042-Newsletter
  Weekly update for SG2042 ecosystem. RISC-V is inevitable!
  ☆22Updated this week
• rvkrypto / rvkrypto-fips
  [HISTORICAL] FIPS and higher-level algorithm tests for RISC-V Crypto Extension
  ☆26Updated 5 months ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆29Updated last month
• riscv-non-isa / riscv-c-api-doc
  Documentation of the RISC-V C API
  ☆74Updated this week
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆83Updated 2 weeks ago
• OpenXiangShan / nexus-am
  ☆32Updated this week
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆39Updated this week