Alternatives and similar repositories for thead-extension-spec

Users that are interested in thead-extension-spec are comparing it to the libraries listed below

• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆40Updated last year
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆40Updated last year
• cnrv / RVSC2023
  RISC-V Summit China 2023
  ☆40Updated last year
• XUANTIE-RV / xuantie-gnu-toolchain
  GNU toolchain for Xuantie RISC-V CPU, including GCC and Binutils ……
  ☆101Updated 5 months ago
• riscv-non-isa / riscv-c-api-doc
  Documentation of the RISC-V C API
  ☆77Updated this week
• riscvarchive / riscv-CMOs
  ☆90Updated 2 weeks ago
• riscv / riscv-aia
  ☆95Updated 2 weeks ago
• riscv / riscv-test-env
  ☆50Updated 4 months ago
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆151Updated last year
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆62Updated 3 years ago
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆52Updated 8 months ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆88Updated last week
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆108Updated last week
• XUANTIE-RV / qemu
  Qemu for Xuantie RISC-V CPU, a generic machine emulator and virtualizer.
  ☆45Updated last month
• riscv-non-isa / riscv-semihosting
  ☆32Updated this week
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆70Updated last year
• RISCVtestbed / rvv-rollback
  Translate RISC-V Vector Assembly from v1.0 to v0.7
  ☆34Updated last year
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 9 months ago
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆89Updated 3 months ago
• RISCV-on-Microsemi-FPGA / FreeRTOS
  FreeRTOS for RISC-V
  ☆27Updated 6 years ago
• riscvarchive / riscv-code-size-reduction
  ☆147Updated last year
• riscv / riscv-plic-spec
  PLIC Specification
  ☆146Updated 2 weeks ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆109Updated 2 weeks ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆102Updated last month
• OpenXiangShan / nexus-am
  ☆36Updated 3 weeks ago
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆193Updated last month
• riscv-admin / riscv-ovpsim
  ☆61Updated 4 years ago
• XUANTIE-RV / buildroot
  Buildroot customized for Xuantie™ RISC-V CPU
  ☆46Updated 3 years ago
• pulp-platform / trdb
  RISC-V processor tracing tools and library
  ☆16Updated last year