Alternatives and similar repositories for v8:

Users that are interested in v8 are comparing it to the libraries listed below

• riscv / riscv-j-extension
  Working Draft of the RISC-V J Extension Specification
  ☆184Updated 2 months ago
• riscv-software-src / riscv-angel
  JavaScript RISC-V ISA Simulator. Boots linux in a web-browser.
  ☆342Updated 4 years ago
• riscvarchive / riscv-software-list
  The RISC-V software tools list, as seen on riscv.org
  ☆461Updated 4 years ago
• michaeljclark / rv8
  RISC-V simulator for x86-64
  ☆702Updated 3 years ago
• rsd-devel / rsd
  RSD: RISC-V Out-of-Order Superscalar Processor
  ☆1,065Updated last month
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆366Updated last year
• riscvarchive / risc-v-getting-started-guide
  The official RISC-V getting started guide
  ☆201Updated last year
• ISRC-CAS / v8-riscv
  PLCT实验室 V8 for RISC-V 的主仓库。2020年完成部署。
  ☆23Updated 4 years ago
• riscvarchive / riscv-binutils-gdb
  RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
  ☆150Updated 2 years ago
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆149Updated this week
• openpower-cores / a2i
  ☆247Updated 2 years ago
• lastmjs / wasm-metal
  A bare metal physical implementation of WebAssembly. That's right, a WebAssembly CPU.
  ☆369Updated 3 years ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆224Updated 4 months ago
• riscvarchive / riscv-gcc
  ☆369Updated last year
• stevehoover / warp-v
  WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  ☆235Updated last month
• westerndigitalcorporation / RISC-V-Linux
  This repository provides a Linux kernel bootable on RISC-V boards from SiFive
  ☆166Updated 5 years ago
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆223Updated last year
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆210Updated last year
• skyzh / RISCV-Simulator
  💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visu…
  ☆201Updated 4 years ago
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆483Updated last month
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆266Updated this week
• riscvarchive / riscv-platform-specs
  RISC-V Profiles and Platform Specification
  ☆113Updated last year
• riscvarchive / educational-materials
  Educational materials for RISC-V
  ☆224Updated 4 years ago
• nbdd0121 / r2vm
  Rust RISC-V Virtual Machine
  ☆97Updated 5 months ago
• OpenXiangShan / NEMU
  ☆272Updated this week
• riscvarchive / riscv-code-size-reduction
  ☆150Updated last year
• riscv-software-src / riscv-pk
  RISC-V Proxy Kernel
  ☆623Updated 3 weeks ago
• nickmqb / wyre
  Hardware definition language that compiles to Verilog
  ☆106Updated 3 years ago
• twilco / riscv-from-scratch
  The code for the RISC-V from scratch blog post series.
  ☆88Updated 4 years ago
• riscv / riscv-crypto
  RISC-V cryptography extensions standardisation work.
  ☆386Updated last year