Alternatives and similar repositories for v8

Users that are interested in v8 are comparing it to the libraries listed below

• riscv / riscv-j-extension
  Working Draft of the RISC-V J Extension Specification
  ☆191Updated 2 weeks ago
• lastmjs / wasm-metal
  A bare metal physical implementation of WebAssembly. That's right, a WebAssembly CPU.
  ☆370Updated 4 years ago
• riscvarchive / risc-v-getting-started-guide
  The official RISC-V getting started guide
  ☆202Updated last year
• riscvarchive / riscv-software-list
  The RISC-V software tools list, as seen on riscv.org
  ☆470Updated 4 years ago
• piranna / wasmachine
  Put WebAssembly in your washing machine
  ☆210Updated 7 years ago
• openpower-cores / a2i
  ☆247Updated 3 years ago
• westerndigitalcorporation / RISC-V-Linux
  This repository provides a Linux kernel bootable on RISC-V boards from SiFive
  ☆169Updated 5 years ago
• andrescv / jupiter
  RISC-V Assembler and Runtime Simulator
  ☆431Updated last year
• MoonbaseOtago / vroom
  VRoom! RISC-V CPU
  ☆509Updated last year
• ISRC-CAS / v8-riscv
  PLCT实验室 V8 for RISC-V 的主仓库。2020年完成部署。
  ☆24Updated 5 years ago
• michaeljclark / rv8
  RISC-V simulator for x86-64
  ☆710Updated 3 years ago
• riscvarchive / riscv-platform-specs
  RISC-V Profiles and Platform Specification
  ☆114Updated last year
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆215Updated last year
• riscv-software-src / riscv-angel
  JavaScript RISC-V ISA Simulator. Boots linux in a web-browser.
  ☆348Updated 5 years ago
• vmware-archive / cascade
  A Just-In-Time Compiler for Verilog from VMware Research
  ☆446Updated 4 years ago
• riscvarchive / riscv-gcc
  ☆372Updated 2 years ago
• riscvarchive / riscv-binutils-gdb
  RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
  ☆150Updated 3 years ago
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆153Updated 3 weeks ago
• riscvarchive / riscv-code-size-reduction
  ☆147Updated last year
• os-fpga / 1st-CLaaS
  Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications
  ☆204Updated this week
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆495Updated last month
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆276Updated this week
• stevehoover / warp-v
  WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  ☆240Updated 3 months ago
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆226Updated last year
• riscvarchive / educational-materials
  Educational materials for RISC-V
  ☆223Updated 4 years ago
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆374Updated last year
• riscv / riscv-crypto
  RISC-V cryptography extensions standardisation work.
  ☆396Updated last year
• riscv-non-isa / riscv-c-api-doc
  Documentation of the RISC-V C API
  ☆77Updated last month
• shady831213 / terminus
  A riscv isa simulator in rust.
  ☆65Updated last year
• fernandotcl / TinyEMU
  Tweaks to Fabrice Bellard's TinyEMU
  ☆136Updated last year