A riscv isa simulator in rust.
☆65Feb 9, 2026Updated 3 weeks ago
Alternatives and similar repositories for terminus
Users that are interested in terminus are comparing it to the libraries listed below
Sorting:
- 可运行OS的RISCV-64的硬件模拟器设计与实现☆23Mar 26, 2021Updated 4 years ago
- Rust support for RISC-V Platform-Level Interrupt Controller☆10Oct 13, 2022Updated 3 years ago
- ☆13Jul 26, 2021Updated 4 years ago
- Decaf 实验综述☆12Jan 7, 2020Updated 6 years ago
- 实现和扩展RISC-V SBI运行时，使之能够支持并运行操作系统☆14Apr 1, 2025Updated 11 months ago
- 各类内核的设计思路☆19May 19, 2021Updated 4 years ago
- RISC-V Proxy Kernel for Education☆28Dec 5, 2023Updated 2 years ago
- The virtual console embedded in rCore kernel.☆11May 6, 2025Updated 9 months ago
- RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).☆939May 29, 2024Updated last year
- 操作系统课程实验设计☆12Mar 16, 2025Updated 11 months ago
- SIMD aligned data structures to work with `std::simd`.☆11Dec 14, 2024Updated last year
- 项目的主仓库☆26Sep 11, 2022Updated 3 years ago
- ☆32Jan 21, 2026Updated last month
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Aug 28, 2023Updated 2 years ago
- rCore_tutorial_tests☆11Aug 8, 2021Updated 4 years ago
- A fast ring buffer implementation with cheap and safe indexing written in Rust☆15Sep 22, 2025Updated 5 months ago
- RISC-V V Extension Encoder☆11Jul 28, 2022Updated 3 years ago
- An implementation of ext2 filesystem in Rust☆15Oct 8, 2021Updated 4 years ago
- "全国大学生操作系统比赛2026"相关信息☆280Jan 4, 2026Updated 2 months ago
- ☆75May 9, 2022Updated 3 years ago
- RISC-V processor emulator written in Rust+WASM☆678Apr 6, 2023Updated 2 years ago
- [AFK] Hardware router in Chisel (THU Network Joint Lab 2020)☆14Oct 8, 2020Updated 5 years ago
- ☆17Feb 20, 2026Updated last week
- TensorFlow Lite for BL602☆12Jun 22, 2021Updated 4 years ago
- GDB Stub for RT-Thread(already in RT-Thread master)☆17Jan 10, 2015Updated 11 years ago
- [WIP] Tutorial for zCore kernel.☆59Aug 28, 2021Updated 4 years ago
- Scripts to automate building linux images for my emulator riscv_em☆16Oct 24, 2023Updated 2 years ago
- Asynchronous OS kernel written in Rust.☆32Nov 27, 2020Updated 5 years ago
- 快速陷入处理☆39Jan 22, 2026Updated last month
- 一组面向普通大学本科生的简单操作系统实验☆30Apr 24, 2023Updated 2 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Feb 17, 2022Updated 4 years ago
- Just A Really Very Impressive Systemverilog UVM Kit☆18Dec 17, 2020Updated 5 years ago
- ☆21May 30, 2025Updated 9 months ago
- 蓝牙协议栈抽象层☆16Oct 14, 2021Updated 4 years ago
- A 5-stage pipelining RISC-V 32I simulator written in Rust.☆19Apr 21, 2021Updated 4 years ago
- Source-level operating system debugging tool that supports debugging kernel and multiple user processes synchronously. VSCode integration…☆37Dec 30, 2025Updated 2 months ago
- Original RISC-V 1.0 implementation. Not supported.☆42Oct 4, 2018Updated 7 years ago
- ☆70Aug 26, 2025Updated 6 months ago
- CS140e without Rust is not CS140e. Sergio Benitez plz come back.☆76Apr 1, 2020Updated 5 years ago