Alternatives and similar repositories for flow-examples:

Users that are interested in flow-examples are comparing it to the libraries listed below

• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆37Updated 3 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆56Updated 3 weeks ago
• lambdaconcept / lambdaUSB
  A configurable USB 2.0 device core
  ☆30Updated 4 years ago
• mmicko / cross-fpga
  Cross compile FPGA tools
  ☆22Updated 4 years ago
• fusesoc / sd_device
  SD device emulator from ProjectVault
  ☆16Updated 5 years ago
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆20Updated 7 years ago
• litex-hub / litehyperbus
  Small footprint and configurable HyperBus core
  ☆11Updated 2 years ago
• lawrie / tiny_ram_soc
  Picorv32 SoC that uses only BRAM, not flash memory
  ☆12Updated 6 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated last year
• TUT-ASI / leon3-grlib-gpl-mirror
  Automated Git mirror of Gaisler's GRLIB/Leon3 releases
  ☆17Updated 2 months ago
• cloudxcc / Arduissimo
  Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).
  ☆20Updated 5 years ago
• olofk / observer
  ☆41Updated 4 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆62Updated last week
• xobs / lxbuildenv
  Simplified environment for litex
  ☆14Updated 4 years ago
• icebreaker-fpga / icebreaker-amaranth-examples
  This repository contains iCEBreaker examples for Amaranth HDL.
  ☆38Updated last year
• mattvenn / logLUTs
  Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.
  ☆20Updated last year
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆37Updated 3 years ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated last year
• ArcaneNibble / KinglerPAR
  Next-Generation FPGA Place-and-Route
  ☆10Updated 6 years ago
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆21Updated 5 years ago
• kazkojima / colorlight-i5-tips
  Tiny tips for Colorlight i5 FPGA board
  ☆56Updated 3 years ago
• sparrowgrine / prjtritium
  ☆22Updated 3 years ago
• daveshah1 / ElasticC
  lightweight open HLS for FPGA rapid prototyping
  ☆20Updated 7 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• bobbl / rudolv
  RISC-V processor
  ☆29Updated 2 years ago
• tomverbeure / jtag_uart_example
  Mini CPU design with JTAG UART support
  ☆19Updated 3 years ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆47Updated 2 months ago
• whitequark / icefloorplan
  iCE40 floorplan viewer
  ☆24Updated 6 years ago
• HarmonInstruments / verilog
  ☆20Updated 2 years ago