Research Interan@BARC FPGA based High-Throughput Generic ECC Implementation in Binary Extension Field
☆23Feb 20, 2017Updated 9 years ago
Alternatives and similar repositories for VerilogCodeECC
Users that are interested in VerilogCodeECC are comparing it to the libraries listed below
Sorting:
- This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…☆31Sep 24, 2018Updated 7 years ago
- Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)☆21Oct 31, 2017Updated 8 years ago
- Implementation of ECC on FPGA-Zynq7000 SoC☆19Jul 12, 2019Updated 6 years ago
- Verilog implementation of the SHA-512 hash function.☆44Jan 17, 2026Updated 2 months ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆22May 12, 2025Updated 10 months ago
- Pure Python implementation of an elliptic curve cryptosystem based on FIPS 186-3. WARNING: This Project is de-facto unmaintained since 20…☆20Nov 20, 2015Updated 10 years ago
- A extremely size-optimized RV32I soft processor for FPGA.☆27Jun 19, 2018Updated 7 years ago
- Verilog implementation of the SHA-1 cryptgraphic hash function☆57Apr 3, 2025Updated 11 months ago
- ☆11Jan 21, 2019Updated 7 years ago
- The working draft to split rocket core out from rocket chip☆14Dec 22, 2023Updated 2 years ago
- Netlist and Verilog Haskell Package☆19Nov 21, 2010Updated 15 years ago
- Project 2.2 Frequency counter☆12May 30, 2025Updated 9 months ago
- Slab allocator for no_std systems. Uses multiple slabs with blocks of different sizes and makes a linked list from free blocks☆13Jul 31, 2023Updated 2 years ago
- SocKit 1-wire (onewire) master☆19Aug 5, 2012Updated 13 years ago
- kenDryte K210 Cloud Build Support☆11Oct 24, 2018Updated 7 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆14Jan 4, 2019Updated 7 years ago
- Universal Advanced JTAG Debug Interface☆17May 10, 2024Updated last year
- Examples of unions, interfaces, and assertions in SystemVerilog☆13Aug 31, 2013Updated 12 years ago
- A set of yasnippets for emacs that assist with SystemVerilog☆11Nov 25, 2011Updated 14 years ago
- 编程百科☆33Mar 15, 2014Updated 12 years ago
- A command-line tool for convert SVG image to PDF file☆17Mar 29, 2025Updated 11 months ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- C implementation of the Kohonen Neural Network (SOM algorithm)☆11May 5, 2019Updated 6 years ago
- Traces for SVA - SystemVerilog Assertions; Will use Go2UVM package to write traces and use uvm_report_mock to predict errors☆11Sep 2, 2016Updated 9 years ago
- prebuild package for cross compiling riscv☆17Dec 28, 2021Updated 4 years ago
- Smoothed z-score algo (very robust thresholding algorithm)☆15Nov 10, 2017Updated 8 years ago
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- Fountain codes implemented in Rust☆17Aug 11, 2020Updated 5 years ago
- ECDSA VHDL Implementation☆12Apr 6, 2018Updated 7 years ago
- learning VHDL☆12Jul 1, 2014Updated 11 years ago
- TEE hardware - based on the chipyard repository - hardware to accelerate TEE☆24Dec 16, 2022Updated 3 years ago
- Hardware Implementation of Sigmoid Function using verilog HDL☆16Dec 16, 2019Updated 6 years ago
- Verilog language support in Atom☆18Jun 30, 2019Updated 6 years ago
- Hardware implementation of the SHA-256 cryptographic hash function☆372Dec 15, 2025Updated 3 months ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆15Jan 9, 2017Updated 9 years ago
- ☆26Jun 21, 2019Updated 6 years ago
- A small and simple rv32i core written in Verilog☆17Jul 29, 2022Updated 3 years ago
- FPGA Development for the parallella☆19Aug 9, 2017Updated 8 years ago
- Multi-Technology RAM with AHB3Lite interface☆25May 10, 2024Updated last year