FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.
☆63Mar 16, 2023Updated 3 years ago
Alternatives and similar repositories for bscan_spi_bitstreams
Users that are interested in bscan_spi_bitstreams are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- XVCD implementation for ANITA. Note that "ftdi_xvc_core.c" is a generic libftdi-based MPSSE XVC handler, and is awesome.☆19Jul 10, 2020Updated 6 years ago
- Xilinx Virtual Cable Daemon☆20Nov 20, 2019Updated 6 years ago
- Basic loadout for SQRL Acorn CLE 215/215+ board. Blinks all LEDs, outputs square waves on all 12 GPIO outputs☆70Nov 21, 2021Updated 4 years ago
- Xilinx 7-series FTDI-FPGA interface through JTAG with 125 us roundtrip latency☆22May 30, 2019Updated 7 years ago
- Some Python scripts to program Xilinx FPGAs using OpenOCD☆25Oct 22, 2016Updated 9 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- iCE40 floorplan viewer☆24Jun 23, 2018Updated 8 years ago
- The original high performance and small footprint system-on-chip based on Migen™☆343Jan 5, 2026Updated 8 months ago
- Wishbone to ARM AMBA 4 AXI☆17May 25, 2019Updated 7 years ago
- Altera JTAG UART wrapper for Bluespec☆26Mar 27, 2014Updated 12 years ago
- Equihash Proof of Work for Node.js☆11Oct 3, 2017Updated 8 years ago
- Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or S…☆289Jun 4, 2026Updated 3 months ago
- A multiply core generator☆16Jun 25, 2020Updated 6 years ago
- Student starter code for Fall 2019 labs☆13Nov 28, 2019Updated 6 years ago
- An Open Source FPGA GroestlCoin Miner☆10Feb 11, 2018Updated 8 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- JESD204B core for Migen/MiSoC☆37May 5, 2021Updated 5 years ago
- https://ve0x10.in/idf-notes-sra/☆13May 27, 2020Updated 6 years ago
- Python interface to PCIE☆41Apr 30, 2018Updated 8 years ago
- USB-JTAG Adapter Using CH552☆73Jan 7, 2022Updated 4 years ago
- ☆26Feb 15, 2025Updated last year
- GDSII manipulation library☆17Dec 13, 2025Updated 9 months ago
- Xilinx Virtual Cable Server for Raspberry Pi☆127Mar 14, 2022Updated 4 years ago
- Implementation of a cache memory in verilog☆14Dec 5, 2017Updated 8 years ago
- A flexible, simple, yet powerful FPGA development board.☆17Feb 7, 2018Updated 8 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Project X-Ray Database: XC7 Series☆77Dec 14, 2021Updated 4 years ago
- Example code for Spresense Arduino development☆14Aug 4, 2020Updated 6 years ago
- FPGA config visualized. demo:☆20Mar 17, 2020Updated 6 years ago
- ☆15Nov 28, 2020Updated 5 years ago
- MyBlaze is a synthesizable clone of the MicroBlaze Soft Processor written in MyHDL (http://www.myhdl.org). It started as a translation of…☆17May 30, 2013Updated 13 years ago
- Automatically exported from code.google.com/p/playtag☆14Jan 9, 2023Updated 3 years ago
- USB Full-Speed/Hi-Speed Device Controller core for FPGA☆34Nov 23, 2020Updated 5 years ago
- A minimal makefile build environment for Xilinx FPGAs☆23Aug 23, 2021Updated 5 years ago
- FPGA USB 1.1 Low-Speed Implementation☆36Oct 3, 2018Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.☆38May 25, 2022Updated 4 years ago
- ☆145Feb 16, 2026Updated 7 months ago
- HDL tools layer for OpenEmbedded☆18Oct 20, 2024Updated last year
- ☆118Jan 22, 2023Updated 3 years ago
- FPGA code for NeTV2☆16Dec 3, 2018Updated 7 years ago
- Trying to port the Analog Discovery into libsigrok☆19Sep 9, 2014Updated 12 years ago
- Project template for wafer.space MPW runs using the gf180mcu PDK☆44Aug 12, 2026Updated last month