qianwk / Some-Collected-Papers-on-Stochastic-Computing
☆15Updated 2 years ago
Alternatives and similar repositories for Some-Collected-Papers-on-Stochastic-Computing
Users that are interested in Some-Collected-Papers-on-Stochastic-Computing are comparing it to the libraries listed below
Sorting:
- Open-source of MSD framework☆16Updated last year
- Stochastic Computing for Deep Neural Networks☆33Updated 4 years ago
- An FPGA Accelerator for Transformer Inference☆81Updated 3 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆65Updated 2 months ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆93Updated 3 years ago
- a Computing In Memory emULATOR framework☆11Updated 11 months ago
- ☆26Updated last month
- A collection of tutorials for the fpgaConvNet framework.☆39Updated 7 months ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆34Updated 2 years ago
- Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)☆14Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆77Updated 3 years ago
- syn script for DC Compiler☆13Updated 3 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆17Updated last year
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆24Updated 3 years ago
- C++ code for HLS FPGA implementation of transformer☆16Updated 8 months ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆48Updated 3 years ago
- Fast Emulation of Approximate DNN Accelerators in PyTorch☆22Updated last year
- A collection of research papers on SRAM-based compute-in-memory architectures.☆28Updated last year
- ☆23Updated last year
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- An HLS based winograd systolic CNN accelerator☆52Updated 3 years ago
- ☆10Updated 5 months ago
- ☆15Updated last year
- A CNN accelerator design inspired by MIT Eyeriss project☆17Updated 3 years ago
- A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC☆28Updated 3 years ago
- Verilog implementation of Softmax function☆65Updated 2 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- ☆15Updated this week
- Sparse CNN Accelerator targeting Intel FPGA☆11Updated 3 years ago
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 4 years ago